74LS11 Search Results

74LS11 Result Highlights (5)

Part	Manufacturer	Description
74LS112P-E	Renesas Electronics Corporation	HD74LS Series
74LS11FPEL-E	Renesas Electronics Corporation	HD74LS Series
74LS11P-E	Renesas Electronics Corporation	HD74LS Series
74LS112FPEL-E	Renesas Electronics Corporation	HD74LS Series
SN74LS11D	Texas Instruments	Triple 3-input positive-AND gates 14-SOIC 0 to 70

74LS11 Price and Stock

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Texas Instruments SN74LS11NSR IC GATE AND 3CH 3-INP 14SO
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	SN74LS11NSR	Cut Tape	1,968		1	1 $0.81 10 $0.578 100 $0.456 1000 $0.39221 10000 $0.39221	Buy Now
	SN74LS11NSR	Digi-Reel	1,968		1	1 $0.81 10 $0.578 100 $0.456 1000 $0.39221 10000 $0.39221	Buy Now
Mouser Electronics	SN74LS11NSR		1,772			1 $0.81 10 $0.52 100 $0.426 1000 $0.393 10000 $0.352	Buy Now
Texas Instruments SN74LS112ANSR IC FF JK TYPE DUAL 1BIT 16SO
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	SN74LS112ANSR	Digi-Reel	1,933		1	1 $0.78 10 $0.556 100 $0.4381 1000 $0.37644 10000 $0.37644	Buy Now
	SN74LS112ANSR	Cut Tape	1,933		1	1 $0.78 10 $0.556 100 $0.4381 1000 $0.37644 10000 $0.37644	Buy Now
	SN74LS112ANSR	Reel			2,000	1 - 10 - 100 - 1000 - 10000 $0.34414	Buy Now
Mouser Electronics	SN74LS112ANSR		1,916			1 $0.78 10 $0.5 100 $0.409 1000 $0.377 10000 $0.337	Buy Now
Texas Instruments SN74LS11DR IC GATE AND 3CH 3-INP 14SOIC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	SN74LS11DR	Digi-Reel	1,145		1	1 $0.66 10 $0.471 100 $0.3694 1000 $0.31606 10000 $0.31606	Buy Now
	SN74LS11DR	Cut Tape	1,145		1	1 $0.66 10 $0.471 100 $0.3694 1000 $0.31606 10000 $0.31606	Buy Now
Mouser Electronics	SN74LS11DR		2,500			1 $0.61 10 $0.42 100 $0.344 1000 $0.312 10000 $0.276	Buy Now
Rochester Electronics	SN74LS11DR		87,458		1	1 $0.2931 10 $0.2931 100 $0.2755 1000 $0.2491 10000 $0.2491	Buy Now
Texas Instruments SN74LS112AD IC FF JK TYPE DUAL 1BIT 16SOIC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	SN74LS112AD	Tube	769		1	1 $0.83 10 $0.596 100 $0.83 1000 $0.41962 10000 $0.41962	Buy Now
Rochester Electronics	SN74LS112AD		49,113		1	1 $0.3792 10 $0.3792 100 $0.3564 1000 $0.3223 10000 $0.3223	Buy Now
Texas Instruments SN74LS11D IC GATE AND 3CH 3-INP 14SOIC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	SN74LS11D	Tube	332		1	1 $0.87 10 $0.619 100 $0.4901 1000 $0.45776 10000 $0.45776	Buy Now

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74LS11 Datasheets (44)

Part	Manufacturer	Description	Datasheet Type	PDF
74LS11	Fairchild Semiconductor	Triple 3-Input AND Gate	Original	PDF
74LS11	Fairchild Semiconductor	Full Line Condensed Catalogue 1977	Scan	PDF
74LS11	Unknown	TRIPLE 3-INPUT AND GATE	Scan	PDF
74LS11	Raytheon	Positive-AND Gates	Scan	PDF
74LS11	Signetics	Triple 3-Input NAND / AND Gates	Scan	PDF
74LS11	Signetics	Triple Three-Input NAND / AND Gates	Scan	PDF
74LS11	Signetics	Integrated Circuits Catalogue 1978/79	Scan	PDF
74LS112	Fairchild Semiconductor	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs	Original	PDF
74LS112	Hitachi Semiconductor	Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear)	Original	PDF
74LS112	Motorola	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP	Original	PDF
74LS112	Texas Instruments	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR	Original	PDF
74LS112	Fairchild Semiconductor	Full Line Condensed Catalogue 1977	Scan	PDF
74LS112	Raytheon	Dual J-K Negative-Edge-Triggered Flip-Flops	Scan	PDF
74LS112	Signetics	Dual J-K Edge-Triggered Flip-Flop	Scan	PDF

74LS112	Signetics	Dual J-K Edge Triggered Flip-Flop	Scan	PDF
74LS112	Signetics	Integrated Circuits Catalogue 1978/79	Scan	PDF
74LS112C	Unknown	TTL Data Book 1980	Scan	PDF
74LS112DC	Fairchild Semiconductor	Dual JK Negative Edge Triggered Flip-Flop	Scan	PDF
74LS112FC	Fairchild Semiconductor	Dual JK Negative Edge Triggered Flip-Flop	Scan	PDF
74LS112M	Unknown	TTL Data Book 1980	Scan	PDF

74LS11 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
74LS112A Abstract: 74LS112 SN54/74LS112A truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN JD16 Text: SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the	Original	SN54/74LS112A 74LS112A 74LS112 SN54/74LS112A truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN JD16	PDF
74LS114A Abstract: truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS114 Text: SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be	Original	SN54/74LS114A 74LS114A truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS114	PDF
74 LS 193 Logic DIAGRAM Abstract: truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN Text: SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be	Original	SN54/74LS114A 74LS114A 74 LS 193 Logic DIAGRAM truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN	PDF
M74LS11P Abstract: 20-PIN M74LS11 Text: MITSUBISHI LSTTLs 74LS11P TR IP LE 3 -IN P U T P O S ITIV E AND GATE DESCRIPTION The M 74LS11P is a s e m ico n d u c to r in teg rated c irc u it PIN CONFIGURATION TOP VIEW c o n ta in in g th re e tr ip le -in p u t positive A N D and negative O R gates.	OCR Scan	M74LS11P M74LS11P 16-PIN 20-PIN M74LS11	PDF
ALU IC 74181 Abstract: 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 7411 3 INPUT AND gate TTL 74ls83 pin diagram of 7411 logic diagram of 7432 Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 Vcc Vcc 1^1FH [iä\| [vii Eòi [T\| r»1 füi Fai np f i ! Föi lyi rn	OCR Scan	54H/74H08, 54S/74S08, 54LS/74LS08 54S/74S09, 54LS/74LS09 54H/74H21 54LS/74LS21 54S/74S32 54LS/74LS32 54H/74H11, ALU IC 74181 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 7411 3 INPUT AND gate TTL 74ls83 pin diagram of 7411 logic diagram of 7432	PDF
74S113D Abstract: 74LS113D Text: 113 C O N N E C T IO N DIAGRAM P IN O U T A 548/748113 * 54LS/74LS113 ö / / « 7 DUAL JK EDGE-TRIGGERED FLIP-FLOP D ESCRIPTION — T h e ’ 113 o ffe rs in d iv id u a l J, K, Set an d C lo c k inputs. W hen the c lo c k g o e s H IG H the in p u ts are e n a b le d and data m ay be entered.	OCR Scan	54LS/74LS113 54/74LS 54/74S 74S113D 74LS113D	PDF
Untitled Abstract: No abstract text available Text: LS TTL DN74LS Series 74LS11 74LS11 D^74LS11 Triple 3-input P ositive AND Gates • Description P-1 D N 74L S 11 contains three 3-input positive isolation AND gate circuits. I Features • Low pow er consum ption P d = 13mW typical • High speed ( t pii = 9ns typical)	OCR Scan	DN74LS DN74LS11 DN74LS11 74LS11 14-pin SO-14D) MA161.	PDF
74LS113 Abstract: C0056 Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. Th e asynchro nous S e t Sq input, w hen LOW , forces	OCR Scan	74LS113, 1N916, 1N3064, 500ns 500ns 74LS113 C0056	PDF
74ls112 pin configuration Abstract: 74ls112 function table 74LS112 74S112 Text: Signetics 74LS112, S112 Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set So and Reset (R q) inputs, when LOW,	OCR Scan	74LS112, 1N916, 1N3064, 500ns 500ns 74ls112 pin configuration 74ls112 function table 74LS112 74S112	PDF
Untitled Abstract: No abstract text available Text: SN 54LS112A , S N 54S 112, SN 74LS112A , S N 74S 112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS W ITH PRESET AND CLEAR D 2 6 6 1 . APRIL 1 9 8 2 - REVISED M A R C H 1 9 8 8 Fully Buffered to Offer Maximum Isolation from External Disturbance r a a SN 54LS 112A , SN 54S 112 . . . J OR W PACKAGE	OCR Scan	54LS112A 74LS112A	PDF
74ls112 pin diagram Abstract: 74HC112 Text: GD54/74HC112, GD54/74HCT112 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 54/74LS112. They consist of two J-K flip-flops with individual J, K, CLOCK, PRESET, and CLEAR in puts. These flip-flops are edge sensitive to the clock	OCR Scan	GD54/74HC112, GD54/74HCT112 54/74LS112. 74ls112 pin diagram 74HC112	PDF
74LS11 pin configuration Abstract: PIN CONFIGURATION 7411 74ls characteristics 7411 pin configuration N7411F N7411N N74H11F N74H11N N74LS11F N74LS11N Text: 54/7411 54H/74H11 54S/74S11 54LS/74LS11 ORDERING CODE PIN CONFIGURATION See Section 9 for further Package and Ordering Information. C O M M E R C IA L RANGES ± 5%; Ta - 0°C to *70°C PACKAGES PIN CO N F. VCC = 5V P lastic DIP Fig. A Fig. A N 741 1 N N74S11N	OCR Scan	54H/74H11 54S/74S11 54LS/74LS11 N7411N N74H11N N74S11N N74LS11N N7411F N74H11F N74S11F 74LS11 pin configuration PIN CONFIGURATION 7411 74ls characteristics 7411 pin configuration N7411F N7411N N74LS11F N74LS11N	PDF
74LS113 Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113 Text: 74LS113, S 'it e Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J -K n e g a tive e dg e trig g e re d flip -flo p fe a tu rin g individ u a l J, K, S e t a n d C lo c k inp u ts. T h e a s y n c h ro	OCR Scan	74LS113, tr113, 1N916, 1N3064, 500ns 74LS113 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113	PDF
74ls112 pin diagram Abstract: 74LS112 74ls112 pin configuration 74ls112 function table 74ls112 waveform 74LS 74S112 N74LS112D N74LS112N N74S112D Text: 74LS112, S112 S ig n e tic s Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Lo gic P roducts DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and Reset inputs. The Set 3d and Reset (Rq) inputs, when LOW,	OCR Scan	74LS112, 1N916, 1N3064, 500ns 74ls112 pin diagram 74LS112 74ls112 pin configuration 74ls112 function table 74ls112 waveform 74LS 74S112 N74LS112D N74LS112N N74S112D	PDF

so 54 t Abstract: 74ls 3-input and gate TTL IC 74 SN74LS 74LS11 Motorola 74LS TTL 74LS11 74ls11 ic for IC 74LS11 all gate ic data 74 Text: M MOTOROLA SN54/74LS11 TRIPLE 3-INPUT AND GATE TRIPLE 3-INPUT AND GATE v cc un r¡7j rrii rm nói m LOW POWER SCHOTTKY rn =§y n J SUFFIX C E R A M IC C A SE 632-08 14 GND 1 N SUFFIX PLA S TIC C A SE 646-06 D SUFFIX 14 1 SO IC C A S E 751A-02 5 ORDERING INFORMATION	OCR Scan	SN54/74LS11 51A-02 SN54/74LS so 54 t 74ls 3-input and gate TTL IC 74 SN74LS 74LS11 Motorola 74LS TTL 74LS11 74ls11 ic for IC 74LS11 all gate ic data 74	PDF
74LS113A Abstract: tp 2123 Text: MITSUBISHI LSTTLs M 7 4LS 113 A P DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS113A P c o n ta in in g 2 J -K is a sem ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits	OCR Scan	74LS113A b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN tp 2123	PDF
Untitled Abstract: No abstract text available Text: <8> MOTOROLA SN54/74LS114A D E S C R IPT IO N — The SN 54LS/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data w ill be accepted. The logic level	OCR Scan	SN54/74LS114A 54LS/74LS114A	PDF
Untitled Abstract: No abstract text available Text: MITSUBISHI LSTTLs M 74LS112AP DUAL J-K N EG A TIVE EDGE-TRIGGERED F L IP FLOPS W IT H SET AND RESET DESCRIPTION The M 7 4L S 11 2A P is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T , J and K inputs	OCR Scan	74LS112AP b2LHfl27 0013Sbl	PDF
Untitled Abstract: No abstract text available Text: GD54/74LS112 DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS WITH SET AND RESET Features Pin C o n fig u ra tio n • Negative edge-triggering • Diode clamped inputs • Independent input/output terminals for each flip-flop. • Direct set and reset inputs • Q and Q outputs	OCR Scan	GD54/74LS112	PDF
74LS114 Abstract: 74ls114d 74S114DC Text: 114 C O N N E C T IO N D IA G R A M PINOUT A •01 ! .54S/74S114 54LS/74LS114 D I / ö H p 003 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP c5{T 1 4 ] Vcc k , T (With Common Clocks and Clears K, C P J i CO S pi Qi Qi Ji[ T n ] cp m D E S C R IP T IO N — The '114 features individual J, K and set inputs and com	OCR Scan	54S/74S114 54LS/74LS114 54/74LS 54/74S 54/74L 74LS114 74ls114d 74S114DC	PDF
74LS11 Abstract: 74S11 54ls11 Text: S N 54LS11, SN54S11, SN 74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE AND GATES A PRIL 19 85 —R EV ISED MARCH 1988 S N 5 4 L S 1 1 . S N 7 4 S 1 1 . . . J OR W P A C K A G E SN 74LS11. SN 74S11 c 1 U 14 : 13 : 2 12 q 3 11 : c4 10 c 5 9 : c6 1A c IB Dependable Texas Instruments Quality and	OCR Scan	54LS11, SN54S11, 74LS11, SN74S11 74LS11 74LS11. 74S11 54ls11	PDF
Untitled Abstract: No abstract text available Text: 112 CONNECTION DIAGRAM P IN O U T A 54S/74S112 t1" 00 \/&4LS/74LS112 b DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The '112 features individual J, K, C lo ck and asynchronous Set and C lear inputs to each flip-flop. When the clo ck goes HIGH, the inputs	OCR Scan	54S/74S112 4LS/74LS112 54/74LS 54/74S	PDF
74LS113 Abstract: No abstract text available Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro nous Set S d input, w hen LOW, forces	OCR Scan	74LS113, 1N916, 1N3064, 500ns 500ns 74LS113	PDF
Untitled Abstract: No abstract text available Text: M O T O R O LA . SN54/74LS11 r r r r r m r TRIPLE 3-INPUT A N D G ATE "L 3 U LiJ U LiJ H I LlJ LO W POWER SCHO TTKY J Suffix — Case 632-08 Ceramic N Suffix — Case 646-06 (Plastic) GUARANTEED OPERATING RANGES SYM B O L MIN TYP MAX UNIT Vcc Supply Voltage	OCR Scan	SN54/74LS11	PDF

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74LS11 Search Results

74LS11 Result Highlights (5)

74LS11 Price and Stock

Texas Instruments SN74LS11NSR

Texas Instruments SN74LS112ANSR

Texas Instruments SN74LS11DR

Texas Instruments SN74LS112AD

Texas Instruments SN74LS11D

74LS11 Datasheets (44)

74LS11 Datasheets Context Search

74LS112A

74LS114A

74 LS 193 Logic DIAGRAM

M74LS11P

ALU IC 74181

74S113D

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74LS113

74ls112 pin configuration

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74ls112 pin diagram

74LS11 pin configuration

74LS113

74ls112 pin diagram

so 54 t

74LS113A

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74LS114

74LS11

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74LS113

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