Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    74LS114A Search Results

    SF Impression Pixel

    74LS114A Price and Stock

    Rochester Electronics LLC SN74LS114ADR

    J-K FLIP-FLOP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS114ADR Bulk 2,500
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 $0.14
    		Buy Now

    Semiconductors 74LS114A

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Onlinecomponents.com 74LS114A 3,240
    • 1 $5.91
    • 10 $5.91
    • 100 $1.47
    • 1000 $1.47
    • 10000 $1.47
    		Buy Now

    Semiconductors 74LS114AJS

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Onlinecomponents.com 74LS114AJS 525
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Buy Now

    Motorola Semiconductor Products SN74LS114AN

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Bristol Electronics SN74LS114AN 4,992
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Get Quote
    SN74LS114AN 34
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Get Quote
    Quest Components SN74LS114AN 88
    • 1 $0.75
    • 10 $0.625
    • 100 $0.5
    • 1000 $0.5
    • 10000 $0.5
    		Buy Now
    SN74LS114AN 3,993
    • 1 $0.95
    • 10 $0.95
    • 100 $0.95
    • 1000 $0.38
    • 10000 $0.3325
    		Buy Now

    Mitsubishi Electric M74LS114AP

    IC,FLIP-FLOP,DUAL,J/K TYPE,LS-TTL,DIP,14PIN,PLASTIC (Also Known As: 74LS114AP)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Quest Components M74LS114AP 25
    • 1 $0.75
    • 10 $0.625
    • 100 $0.625
    • 1000 $0.625
    • 10000 $0.625
    		Buy Now
    Find more 74LS114A price and stock on Findchips.com

    74LS114A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74LS114A

    Abstract: truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS114
    Text: SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be


    Original     		PDF SN54/74LS114A 74LS114A truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS114

    74 LS 193 Logic DIAGRAM

    Abstract: truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
    Text: SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be


    Original     		PDF SN54/74LS114A 74LS114A 74 LS 193 Logic DIAGRAM truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN

    74LS08 fan-in

    Abstract: 74LS398 74LS273 74LS14 Hex Inverter definition MC74F579 74LS181 74ls795 74LS299 Decade Up/Down counter 3 State ttl buffer 74LS245
    Text: Selection Information FAST/LS TTL 1 Circuit Characteristics 2 Design Considerations, Testing and Applications Assistance Form 3 FAST Data Sheets 4 LS Data Sheets 5 Reliability Data 6 Package Information Including Surface Mount 7 FAST AND LS TTL DATA CLASSIFICATION


    Original     		PDF 81LS96) 81LS97) 81LS98) 74LS08 fan-in 74LS398 74LS273 74LS14 Hex Inverter definition MC74F579 74LS181 74ls795 74LS299 Decade Up/Down counter 3 State ttl buffer 74LS245

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The S N 54/74LS 114A offers common clock and common d e a r inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be


    OCR Scan     		PDF SN54/74LS114A 54/74LS

    Untitled

    Abstract: No abstract text available
    Text: <8> MOTOROLA SN54/74LS114A D E S C R IPT IO N — The SN 54LS/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data w ill be accepted. The logic level


    OCR Scan     		PDF SN54/74LS114A 54LS/74LS114A

    SN54LS114A

    Abstract: SN54S114 SN74 SN74LS114A SN74S114A LS114
    Text: SN54LS114A, SN54S114, 74LS114A, SN74S114A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK MARCH 1973 —R EV ISED MARCH 1988 SN 54LS114A . SN 54S114 SN 74LS114A . SN 74S114A • Fully Buffered to Offer Maximum Isolation


    OCR Scan     		PDF SN54LS114A, SN54S114, SN74LS114A, SN74S114A SN54S114. SN54LS114A SN54S114 SN74 SN74LS114A LS114

    C350AVB

    Abstract: full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder
    Text: FUJITSU MICROELECTRONICS F U JIT S U wmmm 7flC D B 37MT7bH □D03c]4b 3 • JZ CMOS Gate Array GENERAL INFORMATION The Fujitsu CM O S gate array fam ily consists of tw en tyeight device types which are fabricated w ith advanced silicon gate CMOS technology. And more than 14 devices


    OCR Scan     		PDF 37MT7bH 74LS175 74LS181 74LS183 74LS190 74LS191 74LS192 74LS193 74LS194A 74LS195A C350AVB full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder

    Untitled

    Abstract: No abstract text available
    Text: SN54LS114A. SN54S114, 74LS114A, SN74S114A DUAL J K NEGATIVE EDGE TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK _ MARCH 1973 —REVISED MARCH 1988 • Fully B u ffe re d to O ffe r M a x im u m Isolation


    OCR Scan     		PDF SN54LS114A. SN54S114, SN74LS114A, SN74S114A 54S114 74LS114A 74S114A

    EATON CM20A

    Abstract: A5 GNE mosfet Hall sensor 44e 402 2N8491 FTG 1087 S TRIAC BCR 10km FEB3T smd transistor marking 352a sharp EIA 577 sharp color tv schematic diagram MP-130 M mh-ce 10268
    Text: Table of Contents N E W A R K E L E C T R O N IC S “Where serving you begins even before you call” Newark Electronics is a UNIQUE broadline distributor of electronic components, dedicated to provid­ ing complete service, fast delivery and in-depth inventory. Our main


    OCR Scan     		PDF

    IC AND GATE 7408 specification sheet

    Abstract: 74LS183 74LS96 SN 74168 7486 XOR GATE IC 74LS192 IC 7402, 7404, 7408, 7432, 7400 IC 7486 for XOR gate IC 74183 74LS193 function table
    Text: PLS-EDIF Bidirectional EDIF Netlist Interface to MAX+PLUS Software Data Sheet September 1991, ver. 3 Features u J Provides a bidirectional netlist interface b etw ee n M A X + P L U S and other m ajor C A E softw are packages Sup ports the industry-standard Electronic Design Interchange Format


    OCR Scan     		PDF

    sn 74373

    Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
    Text: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher


    OCR Scan     		PDF

    SN7401

    Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
    Text: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package


    OCR Scan     		PDF 24-lead SN74S474 SN54S475 SN74S475 SN54S482 SN74S482 LCC4270 SN54490 SN74490 SN54LS490 SN7401 sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c

    Untitled

    Abstract: No abstract text available
    Text: g MOTOROLA SN54LS114A 74LS114A D ESCRIPTIO N — The S N 5 4 L S / 7 4 L S 1 14 A offers common clock and common clear inputs and individual J r K, and set inputs. These m onolithic dual flip-flops are designed so that w hen the clock goes HIGH, the inputs are enabled and data w ill be accepted. The logic level


    OCR Scan     		PDF SN54LS114A SN74LS114A

    74LS82

    Abstract: 74LS176 74LS94 74LS286 74ls150 74LS177 74LS116 74ls198 7400 TTL 74ls521
    Text: GOULD 4055916 GOULD SEMICONDUCTOR SEMICONDUCTOR DIV DIV 03E D | 03E MDSSTlb 09920 D UCICmEU T-4 3I-V 7400 TTL Cells •> GOULD CM OS Gate Array and Standard Cell Library Electronics Features General Description • Over 200 functions available. 7400 TTL Cells, a member of Gould’s EXPERT ASIC


    OCR Scan     		PDF

    UAA2001

    Abstract: MC8500 micromodule m68mm19 1N9388 74ALS643 2N6058 MC145026 2N5160 MOTOROLA MC3340 equivalent pn3402
    Text: MOTOROLA Semiconductors THE EUROPEAN MASTER SELECTION 1982 The total num ber of standard Sem iconductor products available from M otorola ex­ ceeds 15 0 0 0 device types. To most of our custom ers this total presents an overw helm ing choice. The European Master Selection lists approxim ately 4 0 0 0 preferred devices that re­


    OCR Scan     		PDF 0HF40 0HF60 0HF80 6FP10 6F100 70HF10 UAA2001 MC8500 micromodule m68mm19 1N9388 74ALS643 2N6058 MC145026 2N5160 MOTOROLA MC3340 equivalent pn3402

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA <8> SN54LS114A 74LS114A DESCRIPTION — The S N 54 L S /7 4 L S 11 4 A offers com m on clock and com m on clear inputs and individual J, K, and set inputs. These m o no lith ic dual flip-flops are designed so th a t w hen the clock goes HIGH, th e inputs are enabled and data w ill be accepted. The logic level


    OCR Scan     		PDF SN54LS114A SN74LS114A

    74LS382

    Abstract: C1602A C350AVB 74LS08 fan-in 74ls517 74LS556 74LS183 74LS86 full adder MB64H 74LS381
    Text: ix u jD U Lu ra n ctiu F U JIT S U _ mmm CWiOS Gate Array GENERAL INFORMATION The Fujitsu CMOS gate array family consists of twentyeight devlcs types which are fabricated with advanced silicon gate CMOS technology. And more than 14devlc«s are coming. Fujitsu CMOS gate array are configured In a


    OCR Scan     		PDF veF178 74LS181 74LS190 F191H 74LS191 74LS192 74LS193 74LS194A 74LS195A 74S260 74LS382 C1602A C350AVB 74LS08 fan-in 74ls517 74LS556 74LS183 74LS86 full adder MB64H 74LS381

    74LS167

    Abstract: F199 transistor 74LS382 74LS514 74LS76A 74LS183 transistor b1100 74LS204 74ls171 F199
    Text: L F U J I T S U M ICR OELECTRO N ICS • 76C D 13 374T?b2 0003=170 0 ■ n Î-4 2 -1 1 -0 5 " m zæm F U JIT S U @iÆ<§ ñ w m ^ is s E s i GENERAL INFORMATION •. o f standard SSI's and M STs such as 7 4 L S series are prepared as macros called " F - M A C R G " in the library.


    OCR Scan     		PDF 74LS181 74LS183 74LS190 74LS191 74LS192 74LS193 74LS194A 74LS195A 74S260 74LS261 74LS167 F199 transistor 74LS382 74LS514 74LS76A transistor b1100 74LS204 74ls171 F199

    74LS114A

    Abstract: No abstract text available
    Text: TYPES SN54LS114A, SN54S114, 74LS114A, SN74S114 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK REVISED DECEMBER 1983 Fully Buffered to O ffer M axim um Isolation fro m External Disturbance S N 54L S 114A , S N 5 4 S 1 1 4 . . . J OR W PACKAGE


    OCR Scan     		PDF SN54LS114A, SN54S114, SN74LS114A, SN74S114 74LS114A

    RS flip flop IC

    Abstract: JK flip flop IC Toggle flip flop IC JK flip flop IC diagram T flip flop IC M74LS114AP 20-PIN Reset and Set flip flop IC
    Text: MITSUBISHI LS T T Ls 74LS114AP DUAL J-K NEG ATIVE EDGE-TRIGGERED FLIP FLO P WITH SET, COMMON R E S E T , AND COMMON CLOCK DESCRIPTION PIN CONFIGURATION TOP VIEW The M 7 4L S 11 4A P is a semiconductor integrated circuit containing 2 J-K flip -flo p circuits w ith common terminals


    OCR Scan     		PDF M74LS114AP M74LS114AP b2LHfl27 0013Sbl RS flip flop IC JK flip flop IC Toggle flip flop IC JK flip flop IC diagram T flip flop IC 20-PIN Reset and Set flip flop IC

    Untitled

    Abstract: No abstract text available
    Text: SN54LS114A, SN54S114, 74LS114A, SN74S114A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK M A R C H 1973 — R E V ISE D M A R C H 1988 Fully Buffered to Offer Maximum Isolation from External Disturbance SN 54LS114A . SN 54S114


    OCR Scan     		PDF SN54LS114A, SN54S114, SN74LS114A, SN74S114A 54LS114A 54S114 74LS114A 74S114A

    74LS114AP

    Abstract: No abstract text available
    Text: MITSUBISHI LS T T Ls 74LS114AP DUAL J-K NEG ATIVE EDGE-TRIGGERED FLIP FLO P WITH SET, COMMON R E S E T , AND COMMON CLOCK DESCRIPTION PIN CONFIGURATION TOP VIEW The M 7 4L S 11 4A P is a semiconductor integrated circuit containing 2 J-K flip -flo p circuits w ith common terminals


    OCR Scan     		PDF M74LS114AP M74LS114AP b2LHfl27 0013Sbl 74LS114AP

    logos 4012B

    Abstract: 1LB553 Rauland ETS-003 Silec Semiconductors MCP 7833 4057A transistor sr52 74c912 1TK552 74S485
    Text: L p i > « , * S E m Ic O N VOLUM E 3 INTERNATIONAL INTEGRATED CIRCUITS INDEX 5th EDITION 1985 Revised June 1985 COMPILED AND PUBLISHED BY S E M IC O N IN D E X E S L IM IT E D THE SEMICON INDEX SERIES CONSISTS OF VOLUME 1 TRANSISTOR INDEX VOLUME 2 DIODE & SCR INDEX


    OCR Scan     		PDF TDA1510 TDA1510A logos 4012B 1LB553 Rauland ETS-003 Silec Semiconductors MCP 7833 4057A transistor sr52 74c912 1TK552 74S485