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    74S11 Search Results

    74S11 Result Highlights (2)

    Part ECAD Model Manufacturer Description Download Buy
    SN74S112AN Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70 Visit Texas Instruments Buy
    SN74S113N Rochester Electronics LLC J-K Flip-Flop, S Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14, DIP-14 Visit Rochester Electronics LLC Buy
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    74S11 Price and Stock

    Rochester Electronics LLC 74S112DC

    J-K FLIP-FLOP
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    DigiKey 74S112DC Bulk 37,836 1,025
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    Nexperia BAT74S,115

    DIODE ARR SCHOT 30V 200MA 6TSSOP
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    DigiKey BAT74S,115 Reel 12,000 3,000
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    BAT74S,115 Cut Tape 5,803 1
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    Mouser Electronics BAT74S,115 40,218
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    Rochester Electronics BAT74S,115 450 1
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    TTI BAT74S,115 Reel 9,000
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    Rochester Electronics LLC DM74S11J

    IC GATE AND 3CH 3-INP 14CDIP
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    DigiKey DM74S11J Bulk 8,844 533
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    Rochester Electronics LLC SN74S112AN3

    J-K FLIP-FLOP
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    DigiKey SN74S112AN3 Bulk 2,469 952
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    Rochester Electronics LLC SN74S11D

    IC GATE AND 3-INP
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    DigiKey SN74S11D Bulk 1,970 807
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    Find more 74S11 price and stock on Findchips.com

    74S11 Datasheets (29)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74S11 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74S11 Unknown TRIPLE 3-INPUT AND GATE Scan PDF
    74S11 Signetics Triple 3-Input NAND / AND Gates Scan PDF
    74S11 Signetics Triple Three-Input NAND / AND Gates Scan PDF
    74S11 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74S112 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74S112 Signetics Dual J-K Edge-Triggered Flip-Flop Scan PDF
    74S112 Signetics Dual J-K Edge Triggered Flip-Flop Scan PDF
    74S112 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74S112DC Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    74S112FC Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    74S112PC Fairchild Semiconductor Dual JK Negative Edge Triggered Flip-Flop Scan PDF
    74S113 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74S113 Signetics Dual J-K Edge-Triggered Flip-Flop Scan PDF
    74S113 Signetics Dual J-K Edge Triggered Flip-Flop Scan PDF
    74S113 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74S113DC Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF
    74S113FC Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF
    74S113PC Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF
    74S114 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF

    74S11 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    pj 56 diode

    Abstract: pj 34 diode S112 ECG74 S114 74LS 74S112 74S113 74S114 ECG74S74
    Text: S y lv a n ia ECG S e m ic o n d u c to rs ECG74S74, 74S112, 74S113, 74S114 Dual Flip/Flops M a x R a t i n g s / O p e r a t i n g C o n d itio n s 14 13 74H 74 R A T IN G S S E R IE S S E R IE S M ax im u m A llow able D IO D E 74S H 10 9 6 •2 8 0 " 7 . II


    OCR Scan     		PDF ECG74S74, 74S112, 74S113, 74S114 ECG74S74-" pj 56 diode pj 34 diode S112 ECG74 S114 74LS 74S112 74S113 74S114 ECG74S74

    ALU IC 74181

    Abstract: 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 7411 3 INPUT AND gate TTL 74ls83 pin diagram of 7411 logic diagram of 7432
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 Vcc Vcc 1^1FH [iä| [vii Eòi [T| r»1 füi Fai np f i ! Föi lyi rn


    OCR Scan     		PDF 54H/74H08, 54S/74S08, 54LS/74LS08 54S/74S09, 54LS/74LS09 54H/74H21 54LS/74LS21 54S/74S32 54LS/74LS32 54H/74H11, ALU IC 74181 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 7411 3 INPUT AND gate TTL 74ls83 pin diagram of 7411 logic diagram of 7432

    74LS11 pin configuration

    Abstract: PIN CONFIGURATION 7411 74ls characteristics 7411 pin configuration N7411F N7411N N74H11F N74H11N N74LS11F N74LS11N
    Text: 54/7411 54H/74H11 54S/74S11 54LS/74LS11 ORDERING CODE PIN CONFIGURATION See Section 9 for further Package and Ordering Information. C O M M E R C IA L RANGES ± 5%; Ta - 0°C to *70°C PACKAGES PIN CO N F. VCC = 5V P lastic DIP Fig. A Fig. A N 741 1 N 74S11N


    OCR Scan     		PDF 54H/74H11 54S/74S11 54LS/74LS11 N7411N N74H11N N74S11N N74LS11N N7411F N74H11F N74S11F 74LS11 pin configuration PIN CONFIGURATION 7411 74ls characteristics 7411 pin configuration N7411F N7411N N74LS11F N74LS11N

    74S114

    Abstract: ScansUX1001
    Text: FAIRCHILD SUPER HIGH SPEED TTL/SSI . 9S114/54S114, 74S114 DUAL JK EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The 9S114/54S114, 74S114 o ffe r common clock and common clear inputs and individual J, K, and preset inputs. These m on o lith ic dual flip -flop s are designed so th a t when the clock goes HIG H , the inputs are enabled and data w ill be accepted. The logic


    OCR Scan     		PDF 9S114/54S114, 74S114 ScansUX1001

    74LS114

    Abstract: 74ls114d 74S114DC
    Text: 114 C O N N E C T IO N D IA G R A M PINOUT A •01 ! .54S/74S114 54LS/74LS114 D I / ö H p 003 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP c5{T 1 4 ] Vcc k , T (With Common Clocks and Clears K, C P J i CO S pi Qi Qi Ji[ T n ] cp m D E S C R IP T IO N — The '114 features individual J, K and set inputs and com­


    OCR Scan     		PDF 54S/74S114 54LS/74LS114 54/74LS 54/74S 54/74L 74LS114 74ls114d 74S114DC

    74LS11

    Abstract: 74S11 54ls11
    Text: S N 54LS11, SN54S11, SN 74LS11, 74S11 TRIPLE 3-INPUT POSITIVE AND GATES A PRIL 19 85 —R EV ISED MARCH 1988 S N 5 4 L S 1 1 . S N 7 4 S 1 1 . . . J OR W P A C K A G E SN 74LS11. SN 74S11 c 1 U 14 : 13 : 2 12 q 3 11 : c4 10 c 5 9 : c6 1A c IB Dependable Texas Instruments Quality and


    OCR Scan     		PDF 54LS11, SN54S11, 74LS11, SN74S11 74LS11 74LS11. 74S11 54ls11

    Untitled

    Abstract: No abstract text available
    Text: 112 CONNECTION DIAGRAM P IN O U T A 54S/74S112 t1" 00 \/&4LS/74LS112 b DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The '112 features individual J, K, C lo ck and asynchronous Set and C lear inputs to each flip-flop. When the clo ck goes HIGH, the inputs


    OCR Scan     		PDF 54S/74S112 4LS/74LS112 54/74LS 54/74S

    3S114

    Abstract: 74S112
    Text: Sylvan ia ECG Sem ico nd ucto rs ECG74S74, 74S112, 74S113, 74S114 Dual Flip/Flops M ax R atings/O perating Conditions 74H 74 R A T IN G S S E R IE S M aximum Allowable 14 13 12 S E R IE S 7 7 4 LS S E R IE S D IO D E E M IT T E R IN PU T S IN PU TS 7 7 7 74S


    OCR Scan     		PDF ECG74S74, 74S112, 74S113, 74S114 3S114 74S112

    CI 74LS08

    Abstract: 7432 TTL fairchild TTL 7421 74LS21 ttl 7432 TTL 74ls32 TTL 7409 TTL 7486 TTL 74ls86 TTL 7432 fairchild
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS D IG IT A L-T T L D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi


    OCR Scan     		PDF 54H/74H08, 54S/74S08, 54LS/74LS08 54S/74S09, 54LS/74LS09 54H/74H21 54LS/74LS21 54S/74S32 54LS/74LS32 54H/74H11, CI 74LS08 7432 TTL fairchild TTL 7421 74LS21 ttl 7432 TTL 74ls32 TTL 7409 TTL 7486 TTL 74ls86 TTL 7432 fairchild

    SN54LS114A

    Abstract: SN54S114 SN74 SN74LS114A SN74S114A LS114
    Text: SN54LS114A, SN54S114, SN74LS114A, 74S114A DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR, AND COMMON CLOCK MARCH 1973 —R EV ISED MARCH 1988 SN 54LS114A . SN 54S114 SN 74LS114A . SN 74S114A • Fully Buffered to Offer Maximum Isolation


    OCR Scan     		PDF SN54LS114A, SN54S114, SN74LS114A, SN74S114A SN54S114. SN54LS114A SN54S114 SN74 SN74LS114A LS114

    74S112

    Abstract: 54S112 ScansUX1001
    Text: FAIRCHILD SUPER HIGH SPEED TTL/SSI • 9S112/54S112, 74S112 DUAL JK EDGE-TRIGGERED FLIP-FLOP DESCRIPTION — The 9S112/54S 112, 74S112 dual J K flip -flo p s feature individual J, K, clock, and asynchronous preset and clear inputs to each flip -flo p . When the clock goes H IG H , the inputs are enabled and data w ill be accepted. The logic level o f the J and K inputs may be


    OCR Scan     		PDF 9S112/54S112, 74S112 54S112 ScansUX1001

    logic diagram of 7432

    Abstract: CI 7408 TTL 7486 7408 s.i 7408 FL 9014 7486 nor CI 74LS08 7408 fairchild 7432 TTL
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi lyi rn


    OCR Scan     		PDF 54H/74H08, 54S/74S08, 54LS/74LS08 54S/74S09, 54LS/74LS09 54H/74H21 54LS/74LS21 54S/74S32 54LS/74LS32 54H/74H11, logic diagram of 7432 CI 7408 TTL 7486 7408 s.i 7408 FL 9014 7486 nor CI 74LS08 7408 fairchild 7432 TTL

    TTL 7486

    Abstract: FL 9014 TTL 7421 ttl 7432 TTL 7411 TTL 7409 7486 TTL 7411 74LS86 74LS08
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1 FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi ly i r n


    OCR Scan     		PDF 54H/74H08, 54S/74S08, 54LS/74LS08 54S/74S09, 54LS/74LS09 54H/74H21 54LS/74LS21 54S/74S32 54LS/74LS32 54H/74H11, TTL 7486 FL 9014 TTL 7421 ttl 7432 TTL 7411 TTL 7409 7486 TTL 7411 74LS86 74LS08

    7411 3 INPUT AND gate

    Abstract: 74LS11 dm 7411 3 input and gate 7411 74LS11 pinout 7411 and gate 74S11PC 54H11 54S11DM 74H11DC
    Text: 11 CO NNECTIO N DIAGRAMS PINOUT A ^ 4 /7 4 1 1 o/fc:- £ L 54H/74H11 3 ^ u54S/74S11 o / / 6 5 3 -54LS/74LS11 TRIPLE 3-INPUT AND GATE ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%, T a = 0°C to +70° C Vcc = +5.0 V ±10%,


    OCR Scan     		PDF 54H/74H11 u54S/74S11 -54LS/74LS11 74H11PC 74S11PC, 74LS11 74H11DC 74S11 54H11 7411 3 INPUT AND gate dm 7411 3 input and gate 7411 74LS11 pinout 7411 and gate 74S11PC 54S11DM

    74S113

    Abstract: ScansUX1001
    Text: FAIRCHILD SUPER HIGH SPEED TTL/SSI • 9S113/54S113, 74S113 DUAL JK EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — T he 9 S 1 13 /5 4 S 1 13, 7 4 S 1 13 o ffe r in d iv id u a l J, K , preset, and c lo c k in p u ts. These m o n o lith ic dual flip -flo p s are designed so


    OCR Scan     		PDF 9S113/54S113, 74S113 ScansUX1001

    74LS114

    Abstract: N74LS114F N74LS114N N74S114F N74S114N S54LS114F S54LS114W S54S114F S54S114W 74H 14
    Text: 54S/74S114 54LS/74LS114 DESCRIPTION The "114" is a Dual JK N egative EdgeT rig gered F lip -F lo p fe a tu rin g ind iv id u a l J, K, and Set inpu ts and com m on C lo c k and Reset inputs. The Set S d and Reset (R d ) inputs, w hen LOW, set o r reset th e o u tp u ts


    OCR Scan     		PDF 54S/74S114 54LS/74LS114 54H/74H 54S/74S 54LS/74LS 74LS114 N74LS114F N74LS114N N74S114F N74S114N S54LS114F S54LS114W S54S114F S54S114W 74H 14

    8 pin dip j k flipflop ic

    Abstract: 74LS112P 74LS112D 74LS112PC 74ls112 pin diagram
    Text: NATIONAL SEMICOND {LOGIC} DEE D | b S O H E E • 00b37fl7 S | 112 T-lk-07-0 7 CO NN ECTIO N DIAGRAM PINOUT A 54S/74S112 54LS/74LS112 CPi DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP


    OCR Scan     		PDF 00b37fl7 T-lk-07-0 54S/74S112 54LS/74LS112 54/74S 54/74LS 8 pin dip j k flipflop ic 74LS112P 74LS112D 74LS112PC 74ls112 pin diagram

    ic 7411

    Abstract: ic 7411 g 7411 ic 74LS11D 74LS11
    Text: I bSQliaB NATIONAL SENICOND {LOGIC} G2E D DQt>3b4ö 2 I r^ - / r TI C O N N E C T IO N D IA G R A M S PIN O U T A 54/7411 54H/74H11 54S/74S11 54LS/74LS11 T R IP L E 3-IN PU T A N D G A T E O R D E R IN G C O D E: See Section 9 C O M M E R C IA L G R A D E


    OCR Scan     		PDF 54H/74H11 54S/74S11 54LS/74LS11 74H11PC 74S11PC, 4LS11 74H11DC 74S11DC, 74LS11D 74S11FC, ic 7411 ic 7411 g 7411 ic 74LS11

    74LS114

    Abstract: cpj2 8 pin dip j k flipflop ic
    Text: ' NATIONAL SENICOND -CLOCICJ OSE D | b SO llS S 00^37^1 7 | 114 ~ F m -0 7 -0 7 CO NNECTIO N DIAGRAM PINOUT A 54S/74S114 54LS/74LS114 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP c 5 [T ETL Ki T (With Common Clocks and Clears K i CP J t CO Sd ) Qi Ji [ T Oi


    OCR Scan     		PDF 54S/74S114 54LS/74LS114 54/74S 54/74LS 74LS114 cpj2 8 pin dip j k flipflop ic

    IC TTL 7432

    Abstract: 74LS86 gate diagram 7411 3 INPUT AND gate IC 7432 7411 pin diagram 74LS266 IC 7486 74LS series logic gate symbols FL 9014 TTL 74126
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 D17 9S41 1^1FH [iä| [vii Eòi [T| r»1 Vcc Vcc füi Fai np f i ! Föi lyi rn


    OCR Scan     		PDF 54H/74H08, 54S/74S08, 54LS/74LS08 54S/74S09, 54LS/74LS09 54H/74H21 54LS/74LS21 54S/74S32 54LS/74LS32 54H/74H11, IC TTL 7432 74LS86 gate diagram 7411 3 INPUT AND gate IC 7432 7411 pin diagram 74LS266 IC 7486 74LS series logic gate symbols FL 9014 TTL 74126

    7411 3 INPUT AND gate

    Abstract: 7411 74LS11 7411 and gate pin diagram of 7411 74LS11D 74LS11DC dm 7411 3 input and gate PIN diagram 7411 54H11DM
    Text: 11 CONNECTION DIAGRAMS PINOUT A "54/7411 O / f c : L 54H /74H 11 3 ^ u54S/74S11 o/ / 6 =>3 -5 4 L S /7 4 L S 1 1 ^ TRIPLE 3-IN PU T AND GATE ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C


    OCR Scan     		PDF 54H/74H11 u54S/74S11 -54LS/74LS11 74H11PC 74S11PC, 74LS11 74H11DC 74S11DC, 74LS11DC 54H11DM 7411 3 INPUT AND gate 7411 7411 and gate pin diagram of 7411 74LS11D dm 7411 3 input and gate PIN diagram 7411

    74LS112P

    Abstract: 74LS112D 74ls112 pin diagram 74LS112PC 74LS112 74s112p 74LS112DC 54S112DM 74LS112F 74S112
    Text: 112 C O N N E C T IO N D IA G R A M P IN O U T A /54S/74S112 ö ^ \yt4LS/74LS112 b / / c o t , cpi DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP IN PU TS O U TPU T @ tn @ tn + 1 J K Q L L H H L H L H L H Co Q Ü J c d , So Q T « ]c d 2 £ S d ì [4 tT| cp 2 Qi T


    OCR Scan     		PDF /54S/74S112 \/54LS/74LS112 54/74LS 54/74S S4/74LS 74LS112P 74LS112D 74ls112 pin diagram 74LS112PC 74LS112 74s112p 74LS112DC 54S112DM 74LS112F 74S112

    74S206

    Abstract: 74s201
    Text: 54/74S ELECTRICAL CHARACTERISTICS See Notes - Page 50 INPUT VOLTAGE V|L (V) PARAMETER TEST CONDITIONS LOW LEVEL VÇC~MIN MIN TYP MAX OUTPUT VOLTAGE V|C(V) V|H (V) HIGH LEVEL CLAMP VOLTAGE V çç= M IN VCC = “ IN l|=-18 mA MIN TYP MAX MIN TYP VOH (V) HIGH LEVEL


    OCR Scan     		PDF 54/74S 54/74S00 54/74S02 54/74S03 54/74S04 54/74S05 54/74S260 54/74S280 54/74S301 74S206 74s201

    dy 255

    Abstract: 74s405 H R C M F 2J 225 Fairchild 9960 nixie driver 9614 line driver ci 8602 gn block diagram FJH211 Fairchild msi cul9960 variable frequency circuit diagram using IC 555
    Text: IN THE, BOSTON - 6 17- 4 4 * A SUBSIDiA) ./ OF DUCOMMUN INCORPOfiATED S, MASS vw . JU N E 1 97 S Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the


    OCR Scan     		PDF