Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    N74S113N Search Results

    N74S113N Result Highlights (1)

    Part ECAD Model Manufacturer Description Download Buy
    SN74S113N Rochester Electronics LLC J-K Flip-Flop, S Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14, DIP-14 Visit Rochester Electronics LLC Buy
    SF Impression Pixel

    N74S113N Price and Stock

    Rochester Electronics LLC SN74S113N

    J-K FLIP-FLOP, S SERIES, 2-FUNC,
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74S113N Bulk 4,586 38
    • 1 -
    • 10 -
    • 100 $7.99
    • 1000 $7.99
    • 10000 $7.99
    		Buy Now
    Rochester Electronics SN74S113N 4,586 1
    • 1 $8.07
    • 10 $8.07
    • 100 $7.58
    • 1000 $6.86
    • 10000 $6.86
    		Buy Now

    N74S113N Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Type PDF
    N74S113N Signetics Dual J-K Edge-Triggered Flip-Flop Scan PDF
    N74S113N Signetics Dual J-K Edge Triggered Flip-Flop Scan PDF
    N74S113N Signetics Integrated Circuits Catalogue 1978/79 Scan PDF

    N74S113N Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    transistor C3866

    Abstract: Zener PH SEC E13009 ups circuit schematic diagram 1000w E13007 2 E13007 C3866 power transistor texas ttl 74L505 Transistor C3246
    Text: BID CΚΤ DOLLY L IST L OGO LIST SA F E TY & RELIA ΒL TY ΤΕΚ PIN SYSTE M DIGITA L IC's MEMORIES, MOS CMOS .EC L , TT L MICR OP R OC E SSOR SPE CIA L FUN CTION IC's DIGITAL l LINE AR K ARR AYS LIN E A R IC's (PUR CH ) ΤΕΚ-MADE IC's IC's INDEX (COL ORE D PGS)


    Original     		PDF

    D 8243 HC

    Abstract: SO3A 6164 ram rb1-e N74S00 ITT301 N74S04 B177 55604A CD 5888
    Text: Signetics Integrated Circuits Schottky T T L Schottky T T L 74S Series Introduction S c h o ttk y T T L uses a d io d e cla m p design to ensure th e highest speed possible at T T L lo g ic levels ty p ic a lly 3ns gate p ro p a g a tio n de la y and 9 0 M H z f lip f lo p to g gle rate. H o w ever th e y rem ain c o m p a tib le w ith


    OCR Scan     		PDF N74S00N 55376D N74S02N 55377B N74S03N 55378X N74S04N 55379R N74S05N 5380A D 8243 HC SO3A 6164 ram rb1-e N74S00 ITT301 N74S04 B177 55604A CD 5888

    74LS113

    Abstract: C0056
    Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. Th e asynchro­ nous S e t Sq input, w hen LOW , forces


    OCR Scan     		PDF 74LS113, 1N916, 1N3064, 500ns 500ns 74LS113 C0056

    74LS113

    Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
    Text: 74LS113, S 'it e Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J -K n e g a tive e dg e trig g e re d flip -flo p fe a tu rin g individ u a l J, K, S e t a n d C lo c k inp u ts. T h e a s y n c h ro ­


    OCR Scan     		PDF 74LS113, tr113, 1N916, 1N3064, 500ns 74LS113 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113

    B147

    Abstract: B237 ITT301 N74S00 6164 ram memory 74S189 CD 5888 md 8243 N74S00N N74S02N
    Text: Signetics Integrated Circuits Schottky T T L Schottky T T L 74S Series Introduction S c h o ttk y T T L uses a d io d e cla m p design to ensure th e highest speed possible at T T L lo g ic levels ty p ic a lly 3ns gate p ro p a g a tio n de la y and 9 0 M H z f lip f lo p to g gle rate. H o w ever th e y rem ain c o m p a tib le w ith


    OCR Scan     		PDF N74S00N 55376D N74S02N 55377B N74S03N 55378X N74S04N 55379R N74S05N 5380A B147 B237 ITT301 N74S00 6164 ram memory 74S189 CD 5888 md 8243

    74LS113

    Abstract: No abstract text available
    Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro­ nous Set S d input, w hen LOW, forces


    OCR Scan     		PDF 74LS113, 1N916, 1N3064, 500ns 500ns 74LS113

    74LS113

    Abstract: S113 equivalent
    Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro­ nous Set Su input, when LOW, forces


    OCR Scan     		PDF 74LS113, WF08450S 1N916, 1N3064, 500ns 500ns 74LS113 S113 equivalent

    THERMISTORS nsp 037

    Abstract: Thyristor TAG 9118 ICA 0726 0148 Transformer a1273 y k transistor AM97C11CN transistor SK A1104 PM7A2Q B8708 bzy79 yh 5032
    Text: INDEX OF COMPONENTS A Section/Page No. A.C. Adaptor. Adaptor Kits BNC e tc . Adhesive Tapes. Adhesives, Various. Aerosols.


    OCR Scan     		PDF 200X300X360m THERMISTORS nsp 037 Thyristor TAG 9118 ICA 0726 0148 Transformer a1273 y k transistor AM97C11CN transistor SK A1104 PM7A2Q B8708 bzy79 yh 5032

    ttl nand gate

    Abstract: B237 CD 5888 N74S04 transistor b143 e.s N74S00 ITT301 74s200 N74S00N N74S02N
    Text: Signetics Integrated Circuits Schottky TTL Schottky TTL 74S Series Introduction S c h o ttk y T T L uses a d io d e cla m p design to ensure th e highest speed possible at T T L lo g ic levels ty p ic a lly 3ns gate p ro p a g a tio n de la y and 9 0 M H z f lip f lo p to g gle rate. H o w ever th e y rem ain c o m p a tib le w ith


    OCR Scan     		PDF N74S00N 55376D N74S02N 55377B N74S03N 55378X N74S04N 55379R N74S05N 5380A ttl nand gate B237 CD 5888 N74S04 transistor b143 e.s N74S00 ITT301 74s200

    diode LT 42 PR 3002

    Abstract: 5603A intersil b34 DIODE schottky ic 74s201 mmi 6331 74s188 74S474 74S288 FU 3024 82s141
    Text: Signetics Integrated Circuits Schottky T T L Schottky T T L 74S Series Introduction S c h o ttk y T T L uses a d io d e cla m p design to ensure th e highest speed possible at T T L lo g ic levels ty p ic a lly 3ns gate p ro p a g a tio n de la y and 9 0 M H z f lip f lo p to g gle rate. H o w ever th e y rem ain c o m p a tib le w ith


    OCR Scan     		PDF N74S00N 55376D N74S02N 55377B N74S03N 55378X N74S04N 55379R N74S05N 5380A diode LT 42 PR 3002 5603A intersil b34 DIODE schottky ic 74s201 mmi 6331 74s188 74S474 74S288 FU 3024 82s141

    transistor cross reference

    Abstract: MPT3N40 Westinghouse SCR handbook LT 8224 ZENER DIODE sje389 N9602N npn transistor RCA 467 TFK 7 segment displays PUT 2N6027 delco 466
    Text: C K TBD DOLLY LIST LOGO LIST SAFETY & RELIABLTY TEK PN SYSTEM II DIGITAL IC's MEMORIES. MOS. CM OS.ECL. TTL MICROPROCESSOR SPECIAL FUNCTION IC's DIGITAL / LINEAR ARRAYS LINEAR IC'S (PURCH) TEK-MADE IC’s 3 IC's INDEX (COLORED PGS) INCL PRGMD. SCRND.ETC


    OCR Scan     		PDF

    74LS113

    Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
    Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a d u a l J -K n e g a tive edg e trig g e re d flip -flo p fe a tu rin g ind ivid u a l J, K, S e t and C lo c k inp u ts. T h e a s y n c h ro ­


    OCR Scan     		PDF 74LS113, 1N916, 1N3064, 500ns 74LS113 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113

    74LS113

    Abstract: No abstract text available
    Text: 74LS113, S113 Flip-Flops S ig n e tics Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION TYPE T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. T h e asynchro­ nous S et Sp input, when LO W , forces


    OCR Scan     		PDF 74LS113, 500ns 500ns 1N916, 1N3064, 74LS113