Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    74LS113 Search Results

    74LS113 Datasheets (9)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74LS113 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74LS113 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan PDF
    74LS113 Signetics Dual J-K Edge-Triggered Flip-Flop Scan PDF
    74LS113 Signetics Dual J-K Edge Triggered Flip-Flop Scan PDF
    74LS113 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS113C Unknown TTL Data Book 1980 Scan PDF
    74LS113DC Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF
    74LS113FC Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF
    74LS113PC Fairchild Semiconductor Dual JK Edge Triggered Flip-Flop Scan PDF
    SF Impression Pixel

    74LS113 Price and Stock

    Rochester Electronics LLC SN74LS113ADR

    J-K FLIP-FLOP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LS113ADR Bulk 2,500
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 $0.14
    		Buy Now

    NTE Electronics Inc NTE74LS113

    Low Power Schottky Dual J-k Negative Edge Triggered Flip-flop W/preset 14-lead
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Onlinecomponents.com NTE74LS113 51
    • 1 -
    • 10 -
    • 100 $1.19
    • 1000 $0.865
    • 10000 $0.783
    		Buy Now
    TME NTE74LS113 18 1
    • 1 $1.02
    • 10 $1.02
    • 100 $0.9
    • 1000 $0.84
    • 10000 $0.84
    		Buy Now
    Master Electronics NTE74LS113 51
    • 1 -
    • 10 -
    • 100 $1.19
    • 1000 $0.865
    • 10000 $0.783
    		Buy Now

    Semiconductors 74LS113A

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Onlinecomponents.com 74LS113A 1,365
    • 1 $3.69
    • 10 $3.69
    • 100 $1.03
    • 1000 $0.85
    • 10000 $0.85
    		Buy Now

    Signetics N74LS113N

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Bristol Electronics N74LS113N 82
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 -
    		Get Quote
    Quest Components N74LS113N 944
    • 1 $0.75
    • 10 $0.75
    • 100 $0.75
    • 1000 $0.3125
    • 10000 $0.3125
    		Buy Now
    N74LS113N 5
    • 1 $0.77
    • 10 $0.77
    • 100 $0.77
    • 1000 $0.77
    • 10000 $0.77
    		Buy Now
    N74LS113N 220
    • 1 $3.4554
    • 10 $3.4554
    • 100 $2.3036
    • 1000 $2.1308
    • 10000 $2.1308
    		Buy Now

    NEC Electronics Group UPB74LS113C

    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Bristol Electronics UPB74LS113C 50 6
    • 1 -
    • 10 $0.9375
    • 100 $0.6094
    • 1000 $0.6094
    • 10000 $0.6094
    		Buy Now
    Find more 74LS113 price and stock on Findchips.com

    74LS113 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74LS113A

    Abstract: SN54LSXXXJ truth table NOT gate 74 751A-02 SN74LSXXXD SN74LSXXXN
    Text: SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K


    Original     		PDF SN54/74LS113A 74LS113A 11han SN54LSXXXJ truth table NOT gate 74 751A-02 SN74LSXXXD SN74LSXXXN

    truth table NOT gate 74

    Abstract: 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN t flip-flop 74LS113A
    Text: SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K


    Original     		PDF SN54/74LS113A 74LS113A truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN t flip-flop

    k2645

    Abstract: k4005 U664B mosfet k4005 MB8719 transistor mosfet k4004 SN16880N stk5392 STR451 BC417
    Text: 1 BHIAB Electronics Du som söker besvärliga IC & transistorer, börja Ditt sökande hos oss – vi har fler typer på lager än man rimlingen kan begära av ett företag Denna utgåva visar lagerartiklar men tyvärr saknas priser och viss information Men uppdatering sker kontinuerligt


    Original     		PDF MK135 MK136 MK137 MK138 MK139 MK140 Mk142 MK145 MK155 157kr k2645 k4005 U664B mosfet k4005 MB8719 transistor mosfet k4004 SN16880N stk5392 STR451 BC417

    SKIIP 33 nec 125 t2

    Abstract: skiip 613 gb 123 ct RBS 6302 ericsson SKIIP 513 gb 173 ct THERMISTOR ml TDK 150M pioneer PAL 010a Project Report of smoke alarm using IC 555 doc SKiip 83 EC 125 T1 ericsson RBS 6000 series INSTALLATION MANUAL Ericsson Installation guide for RBS 6302
    Text: Discontinued and Superseded Stock Number History. This document contains Discontinued and Superseded Stock Number History. The information is listed in the following format: Stock Number: The original RS Stock Number of the item. Brief Description: The Invoice Description of the item.


    Original     		PDF 734TL UWEB-MODEM-34 HCS412/WM TLV320AIC10IPFB 100MB NEON250 GA-60XM7E BLK32X40 BLK32X42 SKIIP 33 nec 125 t2 skiip 613 gb 123 ct RBS 6302 ericsson SKIIP 513 gb 173 ct THERMISTOR ml TDK 150M pioneer PAL 010a Project Report of smoke alarm using IC 555 doc SKiip 83 EC 125 T1 ericsson RBS 6000 series INSTALLATION MANUAL Ericsson Installation guide for RBS 6302

    7054F

    Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
    Text: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver


    Original     		PDF 2sc4537 2sc454. 2sc4591 2sc4592 2sc4593 2sc460. 2sc4628 2sc4629 2sc4643 2sc4680 7054F BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557

    74S113D

    Abstract: 74LS113D
    Text: 113 C O N N E C T IO N DIAGRAM P IN O U T A 548/748113 * 54LS/74LS113 ö / / « 7 DUAL JK EDGE-TRIGGERED FLIP-FLOP D ESCRIPTION — T h e ’ 113 o ffe rs in d iv id u a l J, K, Set an d C lo c k inputs. W hen the c lo c k g o e s H IG H the in p u ts are e n a b le d and data m ay be entered.


    OCR Scan     		PDF 54LS/74LS113 54/74LS 54/74S 74S113D 74LS113D

    74LS113

    Abstract: C0056
    Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. Th e asynchro­ nous S e t Sq input, w hen LOW , forces


    OCR Scan     		PDF 74LS113, 1N916, 1N3064, 500ns 500ns 74LS113 C0056

    74LS113

    Abstract: 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113
    Text: 74LS113, S 'it e Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J -K n e g a tive e dg e trig g e re d flip -flo p fe a tu rin g individ u a l J, K, S e t a n d C lo c k inp u ts. T h e a s y n c h ro ­


    OCR Scan     		PDF 74LS113, tr113, 1N916, 1N3064, 500ns 74LS113 1N3064 1N916 74LS 74S113 N74LS113N N74S113N S113

    74LS113A

    Abstract: tp 2123
    Text: MITSUBISHI LSTTLs M 7 4LS 113 A P DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH SET DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS113A P c o n ta in in g 2 J -K is a sem ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits


    OCR Scan     		PDF 74LS113A b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN tp 2123

    74LS113

    Abstract: No abstract text available
    Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro­ nous Set S d input, w hen LOW, forces


    OCR Scan     		PDF 74LS113, 1N916, 1N3064, 500ns 500ns 74LS113

    74LS113

    Abstract: S113 equivalent
    Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '113 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Set and Clock inputs. The asynchro­ nous Set Su input, when LOW, forces


    OCR Scan     		PDF 74LS113, WF08450S 1N916, 1N3064, 500ns 500ns 74LS113 S113 equivalent

    74LS113A

    Abstract: No abstract text available
    Text: AA M O T O R O L A SN54/74LS113A D E S C R IPT IO N — The S N 5 4 L S /7 4 L S 1 13A offers individual J, K, set, and clock inputs. These m onolithic dual flip-flops a re designed so that w h e n th e clock goes HIGH, th e inputs a re enabled and data w ill be


    OCR Scan     		PDF SN54/74LS113A 74LS113A

    JK flip flop IC

    Abstract: JK flip flop IC diagram M74LS113AP Toggle flip flop IC 20-PIN M74LS112AP
    Text: M ITSU B IS H I L S T T L s 74LS113AP D U A L J-K N E G A T IV E E D G E - T R IG G E R E D F L I P F L O P W IT H S E T DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS113A P c o n ta in in g 2 J -K is a sem ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits


    OCR Scan     		PDF M74LS113AP M74LS113AP b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN JK flip flop IC JK flip flop IC diagram Toggle flip flop IC M74LS112AP

    74LS113A

    Abstract: No abstract text available
    Text: <g MOTOROLA. SN54/74LS113A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K


    OCR Scan     		PDF SN54/74LS113A 74LS113A

    74S113PC

    Abstract: 54S113DM
    Text: 1 NATIONAL SEfHCOND -CLOGIO DEE D I tiSGllSE DGbBTfii T T ~ *f¿ - 0 7 -0 7 Fl3 CO N N ECTIO N DIAGRAM PINO UT A 54S /74S 113 54LS /74LS113 D UA L JK E D G E -T R IG G E R E D FLIP-FLOP D ESC R IP TIO N — T h e '1 13offers individual J , K, Set and Clock inputs. When


    OCR Scan     		PDF /74LS113 13offers S/74LS 54/74S 54/74LS fl-07 74S113PC 54S113DM

    74LS113

    Abstract: No abstract text available
    Text: 74LS113, S113 Flip-Flops S ig n e tics Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION TYPE T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. T h e asynchro­ nous S et Sp input, when LO W , forces


    OCR Scan     		PDF 74LS113, 500ns 500ns 1N916, 1N3064, 74LS113

    TC74HC113

    Abstract: No abstract text available
    Text: TC74HC113P/F TC74HC113 P /F DUAL J - K F L IP FLOP WITH CLEAR The TC74HC113 is a high speed CMOS DUAL J—K FLIP FLOP fabricated with silicon gate C 2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintain­ ing the CMOS low power dissipation.


    OCR Scan     		PDF TC74HC113P/F TC74HC113

    Untitled

    Abstract: No abstract text available
    Text: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES


    OCR Scan     		PDF G01341Q 4TLS03 0G13411 HD14070B 1407IB HD14556B HD14558B HD14560B HD14562B HD14072B

    C350AVB

    Abstract: full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder
    Text: FUJITSU MICROELECTRONICS F U JIT S U wmmm 7flC D B 37MT7bH □D03c]4b 3 • JZ CMOS Gate Array GENERAL INFORMATION The Fujitsu CM O S gate array fam ily consists of tw en tyeight device types which are fabricated w ith advanced silicon gate CMOS technology. And more than 14 devices


    OCR Scan     		PDF 37MT7bH 74LS175 74LS181 74LS183 74LS190 74LS191 74LS192 74LS193 74LS194A 74LS195A C350AVB full adder using Multiplexer IC 74150 74LS382 74ls69 T2D 7N IC 74ls147 pin details 74LS396 MB652xxx 651XX 74LS86 full adder

    7472 PIN DIAGRAM

    Abstract: 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 74h106 7476 CI 7473 Jk 7476
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 A 4 — J. 9— 10 So « Q — 2 J U» CP o 1— CD 0—3 ¿ So Q CP 8_ K Ä Q Co —I I_ Vcc = Pin 14 GND = Pin 7 in Ü Q UJ EDGE-TRIGGERED 9 O (9 D58 54H/74H106 D59b 54H/74H108


    OCR Scan     		PDF 54H/74H78 54H/74H106 54S/74S112, 54LS/74LS112 54H/74H108 54S/74S113, 54LS/74LS113 54H/74H73 54H/74H103 54S/74S113 7472 PIN DIAGRAM 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 74h106 7476 CI 7473 Jk 7476

    Untitled

    Abstract: No abstract text available
    Text: _ Sb E D • 7*^237 GOSSflMb 6 3 1 ■ S G T H _ / S T S C S -m O M S O N ^ 7 # H D ^ L [ l © ™ K 3D©i S M 5 4 H C 1 13 M 7 4 H C 113 T -M -0 7 -O 7 DUAL J-K FLIP FLOP WITH PRESET G S-THOMSON ■ HIGH SPEED fMAX= 64 MHz Typ. at V c c = 5V


    OCR Scan     		PDF

    74LS115

    Abstract: 74LS273 74LS189 equivalent 74LS00 QUAD 2-INPUT NAND GATE 74LS265 fan-in and fan out of 7486 74LS93A 74LS181 74LS247 replacement MR 31 relay
    Text: F A IR C H IL D LOW POWER S C H O T T K Y D A TA BOOK ERRATA SHEET 1977 Device Page Item Schematic 2-5 Figure 2-6. Blocking diode in upper right is reversed. Also, diode con­ necting first darlington emitter to output should have series resistor. LS33 5-25


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI HIGH SPEED CMOS M74HC113P/FP/DP DUAL I -K F L IP -F L O P WITH S E T DESCRIPTION T he M 7 4 H C 1 1 3 is a sem ico n d u cto r integrated circu it co n ­ PIN CON FIGURATIO N TOP VIEW sistin g of of tw o n e g a tiv e -e d g e trig g ered J - K flip flops with


    OCR Scan     		PDF M74HC113P/FP/DP 14P2P G--06

    or gate thruth table

    Abstract: No abstract text available
    Text: M54HC113 M74HC113 Æ 7 SCS-THOM SON ^ 7 # R if lQ ^ Q i[ L [ l( g ir [S @ M D ( g i DUAL J-K FLIP FLOP WITH PRESET • HIGH SPEED fMAX= 64 MHz (Typ.) at V c c = 5 V LOW POWER DISSIPATION ICC = 2 at TA = 25° C ■ HIGH NOISE IMMUNITY VniH = V n il= 28% VCc (MIN.)


    OCR Scan     		PDF M54HC113 M74HC113 54/74LS113 M74HC113 M74HC113B1N 54/7AHC113 or gate thruth table