74LS11 |
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Fairchild Semiconductor
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Triple 3-Input AND Gate |
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Original |
PDF
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74LS11 |
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Fairchild Semiconductor
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Full Line Condensed Catalogue 1977 |
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Scan |
PDF
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74LS11 |
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Unknown
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TRIPLE 3-INPUT AND GATE |
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Scan |
PDF
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74LS11 |
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Raytheon
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Positive-AND Gates |
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Scan |
PDF
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74LS11 |
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Signetics
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Triple 3-Input NAND / AND Gates |
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Scan |
PDF
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74LS11 |
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Signetics
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Triple Three-Input NAND / AND Gates |
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Scan |
PDF
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74LS11 |
|
Signetics
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Integrated Circuits Catalogue 1978/79 |
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Scan |
PDF
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74LS112 |
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Fairchild Semiconductor
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Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs |
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Original |
PDF
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74LS112 |
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Hitachi Semiconductor
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Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) |
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Original |
PDF
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74LS112 |
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Motorola
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DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
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Original |
PDF
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74LS112 |
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Texas Instruments
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DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR |
|
Original |
PDF
|
74LS112 |
|
Fairchild Semiconductor
|
Full Line Condensed Catalogue 1977 |
|
Scan |
PDF
|
74LS112 |
|
Raytheon
|
Dual J-K Negative-Edge-Triggered Flip-Flops |
|
Scan |
PDF
|
74LS112 |
|
Signetics
|
Dual J-K Edge-Triggered Flip-Flop |
|
Scan |
PDF
|
|
74LS112 |
|
Signetics
|
Dual J-K Edge Triggered Flip-Flop |
|
Scan |
PDF
|
74LS112 |
|
Signetics
|
Integrated Circuits Catalogue 1978/79 |
|
Scan |
PDF
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74LS112C |
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Unknown
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TTL Data Book 1980 |
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Scan |
PDF
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74LS112DC |
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Fairchild Semiconductor
|
Dual JK Negative Edge Triggered Flip-Flop |
|
Scan |
PDF
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74LS112FC |
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Fairchild Semiconductor
|
Dual JK Negative Edge Triggered Flip-Flop |
|
Scan |
PDF
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74LS112M |
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Unknown
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TTL Data Book 1980 |
|
Scan |
PDF
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