dynamic ram binary cell
Abstract: QBA-1 qab1
Text: VIS Preliminary VG36643241AT CMOS Synchronous Dynamic RAM Description The device is CMOS Synchronous Dynamic RAM organized as 524,288 words x 32 bits x 4 banks. it is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only
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VG36643241AT
86-pin
1G5-0172
dynamic ram binary cell
QBA-1
qab1
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VG36128161
Abstract: VG36128161A VG36128401A VG36128801 VG36128801A
Text: VIS Preliminary VG36128401A VG36128801A VG36128161A CMOS Synchronous Dynamic RAM Description The device is CMOS Synchronous Dynamic RAM organized as 8,388,608 - word x 4 -bit x 4 - bank, 4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. These various organizations
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VG36128401A
VG36128801A
VG36128161A
PC100
PC133
54-pin
VG36128401AT
VG36128161
VG36128161A
VG36128401A
VG36128801
VG36128801A
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A43L0616A
Abstract: A43L0616AV
Text: A43L0616A 512K X 16 Bit X 2 Banks Synchronous DRAM Document Title 512K X 16 Bit X 2 Banks Synchronous DRAM Revision History History Issue Date Remark 0.0 Initial issue December 4, 2000 Preliminary 0.1 Add input/output capacitance specification February 13, 2001
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A43L0616A
A43L0616A
A43L0616AV
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Flash MCp nand DRAM 107-ball
Abstract: SAMSUNG MCP nand sdram mcp KAG00H008M-FGG2 UtRAM Density
Text: Advance Prelimanary MCP MEMORY KAG00H008M-FGG2 MCP Specification of 256Mb NAND*2 and 256Mb Mobile SDRAM -1- Revision 0.1 September 2003 Advance Prelimanary MCP MEMORY KAG00H008M-FGG2 Document Title Multi-Chip Package MEMORY 256M Bit 32Mx8 Nand Flash*2 / 256M Bit(4Mx16x4Banks) Mobile SDRAM
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KAG00H008M-FGG2
256Mb
32Mx8)
4Mx16x4Banks)
128Mb
107-Ball
80x13
Flash MCp nand DRAM 107-ball
SAMSUNG MCP
nand sdram mcp
KAG00H008M-FGG2
UtRAM Density
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PD45128163
Abstract: uPD45128163G5-A75-9JF-E
Text: DATA SHEET MOS INTEGRATED CIRCUIT µPD45128163-E 128M-bit Synchronous DRAM 4-bank, LVTTL Description The µPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152 x 16 × 4 word × bit × bank . The synchronous DRAM achieved high-speed data transfer using the pipeline architecture.
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PD45128163-E
128M-bit
PD45128163
728-bit
54-pin
M01E0107
uPD45128163G5-A75-9JF-E
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dba1
Abstract: VG3617161ET
Text: VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM VIS Description The VG3617161ET is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V
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VG3617161ET
VG3617161ET
288-word
16-bit
50-pin
166MHz,
143MHz,
125MHz
1G5-0189
dba1
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8X13
Abstract: A43L0632
Text: A43L0632 Preliminary 512K X 32 Bit X 2 Banks Synchronous DRAM Document Title 512K X 32 Bit X 2 Banks Synchronous DRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue August 1, 2005 Preliminary August, 2005, Version 0.0 AMIC Technology, Corp.
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A43L0632
MO-205.
8X13
A43L0632
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EDI416S4030A
Abstract: No abstract text available
Text: EDI416S4030A 1M x 16 Bits x 4 Banks Synchronous DRAM FEATURES DESCRIPTION • Single 3.3V power supply The EDI416S4030A is 67,108,864 bits of synchronous high data rate DRAM organized as 4 x 1,048,576 words x 16 bits. Synchronous design allows precise cycle control with the use of system clock,
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EDI416S4030A
EDI416S4030A
83MHz
100MHz)
83MHz)
len471)
EDI416S4030A10SI
1Mx16bitsx4banks
100MHz
EDI416S4030A12SI
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WED416S8030A
Abstract: No abstract text available
Text: WED416S8030A 2M x 16 Bits x 4 Banks Synchronous DRAM FEATURES DESCRIPTION • Single 3.3V power supply The WED416S8030A is 134,217,728 bits of synchronous high data rate DRAM organized as 4 x 2,097,152 words x 16 bits. Synchronous design allows precise cycle control with the use of system clock,
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WED416S8030A
WED416S8030A
83MHz
100MHz)
83MHz)
lengt471)
WED416S8030A10SI
2Mx16bitsx4banks
100MHz
WED416S8030A12SI
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Untitled
Abstract: No abstract text available
Text: ESMT M52D16161A SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION 1.8V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency 1, 2 & 3 Burst Length (1, 2, 4, 8 & full page)
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M52D16161A
16Bit
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M12L64164A
Abstract: No abstract text available
Text: ESMT M12L64164A SDRAM 1M x 16 Bit x 4 Banks Synchronous DRAM FEATURES y y y y y y y y ORDERING INFORMATION PRODUCT NO. JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency 2 & 3
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M12L64164A
M12L64164A-5TG
M12L64164A-6TG
M12L64164A-7TG
M12L64164A-5BG
M12L64164A-6BG
M12L64164A-7BG
200MHz
166MHz
143MHz
M12L64164A
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Untitled
Abstract: No abstract text available
Text: ESMT M52S128324A Revision History Revision 1.0 May. 30 2006 -Original Revision 1.1(Jun. 20 2006) -Modify tRC and tRFC spec Revision 1.2(Mar. 02 2007) - Delete BGA ball name of packing dimensions Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2007
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M52S128324A
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Untitled
Abstract: No abstract text available
Text: ESMT M12L64164A Revision History Revision 1.0 13 Dec. 2001 - Original Revision 1.1 (10 Jan. 2002) - Add -6 spec Revision 1.2 (30 Jan. 2002) - Delete Page44 PACKING DIMENSION 54-LEAD TSOP(II) SDRAM (400mil) (1:4). Revision 1.3 (26 Apr. 2002) - tRFC : 60ns. (Page5)
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Page44
54-LEAD
400mil)
M12L64164A
130mA--
180mA
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E014
Abstract: upd4564163g5a10b
Text: DATA SHEET MOS INTEGRATED CIRCUIT µPD4564441, 4564841, 4564163 64M-bit Synchronous DRAM 4-bank, LVTTL Description The µPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 × 4, 2,097,152 × 8 × 4, 1,048,576 ×16 × 4 word × bit × bank , respectively.
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PD4564441,
64M-bit
864-bit
54-pin
M01E0107
E014
upd4564163g5a10b
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dba1
Abstract: MS82V16520 QFP100-P-1420-0
Text: Dear customers, About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI Semiconductor Co., Ltd. on October 1, 2008.
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K4S561633C
Abstract: K4S561633C-RL
Text: K4S561633C-RL N CMOS SDRAM 16Mx16 SDRAM 54CSP (V DD/V DDQ 3.0V/3.0V & 3.3V/3.3V) Revision 0.7 December 2001 Rev. 0.7 Dec. 2001 K4S561633C-RL(N) CMOS SDRAM Revision History Revision 0.0 (April 4. 2001, Target) • First generation of 256Mb Low Power SDRAM without special function(V DD 3.0V, VDDQ 3.0V).
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K4S561633C-RL
16Mx16
54CSP
256Mb
K4S561633C
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Untitled
Abstract: No abstract text available
Text: WED9LC6816V 256Kx32 SSRAM/4Mx32 SDRAM – External Memory Solution for Texas Instruments TMS320C6000 DSP FEATURES DESCRIPTION Clock speeds: The WED9LC6816V is a 3.3V, 256K x 32 Synchronous Pipeline SRAM and a 4Mx32 Synchronous DRAM array constructed with
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WED9LC6816V
256Kx32
SSRAM/4Mx32
TMS320C6000
WED9LC6816V
4Mx32
4Mx16
TMS320C6201
TMS320C6201
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8X13
Abstract: A43E06321
Text: A43E06321 Preliminary 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM Document Title 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue July 21, 2005 Preliminary July, 2005, Version 0.0
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A43E06321
MO-205.
8X13
A43E06321
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A43E16161
Abstract: A43E16161V
Text: A43E16161 Preliminary 1M X 16 Bit X 2 Banks Low Power Synchronous DRAM Document Title 1M X 16 Bit X 2 Banks Low Power Synchronous DRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue August 2, 2005 Preliminary August, 2005, Version 0.0
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A43E16161
54-pin
A43E16161
A43E16161V
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rca ca 3079
Abstract: RCA 3079 MS82V48540 MS82V48540-7 MS82V48540-8 MT53B768M32D4NQ-053 WT:B
Text: お客様各位 資料中の「沖電気」「ＯＫＩ」等名称の OKI セミコンダクタ株式会社への変更について 2008 年 10 月 1 日を以って沖電気工業株式会社の半導体事業は OKI セミコン ダクタ株式会社に承継されました。 従いまして、本資料中には「沖電気工業株
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FJDS82V48540-01
MS82V48540
216-Word
32-Bit
MS82V48540
536-Row
256-Column
TSOPIITSOPII86-P-400-0
MS82V48540-xTA
rca ca 3079
RCA 3079
MS82V48540-7
MS82V48540-8
MT53B768M32D4NQ-053 WT:B
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Untitled
Abstract: No abstract text available
Text: K4S161622D CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Revision 1.5 September 2000 Samsung Electronics reserves the right to change products or specification without notice. Rev 1.5 Sep. '00 K4S161622D CMOS SDRAM Revision History
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K4S161622D
16bit
K4S161622D-70.
K4S161622D
50-TSOP2-400CF
20MAX
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sdram cmos
Abstract: No abstract text available
Text: CMOS SDRAM K4S28163LD-RF/R 8Mx16 Mobile SDRAM 54CSP VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V, TCSR & PASR Revision 1.0 February 2002 Rev. 1.0 Feb. 2002 K4S28163LD-RF/R CMOS SDRAM Revision History Revision 0.0 (December 8. 2000, Preliminary) • First generation of 128Mb Low Power SDRAM (V DD 2.5V, VDDQ 1.8V).
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K4S28163LD-RF/R
8Mx16
54CSP
128Mb
133MHz,
100MHz,
66MHz.
K4S28163LD-RG/SXX
K4S28163LD-RF/RXX
sdram cmos
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Untitled
Abstract: No abstract text available
Text: K4S161622D-TI/P CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Industrial Temperature Revision 1.0 June 1999 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.0 Jun . 1999 K4S161622D-TI/P
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K4S161622D-TI/P
16bit
K4S161622D
K4S161622D
50-TSOP2-400F
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A45L9332A
Abstract: No abstract text available
Text: A45L9332A Series Preliminary 256K X 32 Bit X 2 Banks Synchronous Graphic RAM Document Title 256K X 32Bit X 2 Banks Synchronous Graphic RAM Revision History History Issue Date Remark 0.0 Initial issue August 21, 2001 Preliminary 0.1 Update AC and DC data specification
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A45L9332A
32Bit
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