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    LOGIC SYMBOL 74LS10 Search Results

    LOGIC SYMBOL 74LS10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    DCL541A01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable Visit Toshiba Electronic Devices & Storage Corporation
    DCL542H01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: High / Output enable Visit Toshiba Electronic Devices & Storage Corporation
    DCL541B01 Toshiba Electronic Devices & Storage Corporation Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: High / Input disable Visit Toshiba Electronic Devices & Storage Corporation

    LOGIC SYMBOL 74LS10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74LS109A

    Abstract: SN54/74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 751B-03
    Text: SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D


    Original     		PDF SN54/74LS109A 74LS109A 751B-03 SN54/74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 751B-03

    SN54/74LS109A

    Abstract: 751B-03 truth table NOT gate 74 74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74ls109
    Text: SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D


    Original     		PDF SN54/74LS109A 74LS109A 751B-03 SN54/74LS109A 751B-03 truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74ls109

    74LS107A

    Abstract: 74LS73A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS73
    Text: SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the


    Original     		PDF SN54/74LS107A 74LS107A 74LS73A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS73

    74LS107* pin and application

    Abstract: 74LS107A 74LS73A 74ls107a motorola 5Bp power truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN
    Text: SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the


    Original     		PDF SN54/74LS107A 74LS107A 74LS73A 74LS107* pin and application 74ls107a motorola 5Bp power truth table NOT gate 74 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN

    Untitled

    Abstract: No abstract text available
    Text: LS10 ZgkNational JQflSemiconductor 54LS10/DM54LS10/DM 74LS10 Triple 3-Input NAND Gates General Description Features This device contains three independent gates each of which performs the logic NAND function. _ • Alternate Military/Aerospace device 54LS10 is available. Contact a National Semiconductor Sales Office/


    OCR Scan     		PDF 54LS10/DM54LS10/DM74LS10 54LS10) 54LS10DMQB, 54LS10FMQB, 54LS10LMQB, DM54LS10J, DM54LS10W, DM74LS10M DM74LS10N

    LM 7410

    Abstract: No abstract text available
    Text: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns


    OCR Scan     		PDF 74LS10 74S10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N LM 7410

    TTL 7410

    Abstract: 74LS11 function table 74LS10 pin configuration TTL 7410 AND propagation delay 7411 signetics
    Text: Signetics I 7410, 7411, LS10, LS11 S10, S11 Gates Logic Products • Triple Three-Input NAND '10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S1Û 3ns 12mA 7411 10ns


    OCR Scan     		PDF 74LS10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N N74LS10D, TTL 7410 74LS11 function table 74LS10 pin configuration TTL 7410 AND propagation delay 7411 signetics

    TTL 7411

    Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
    Text: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA


    OCR Scan     		PDF 74LS10 74S10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N TTL 7411 PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10

    TTL 7410

    Abstract: ua 7411 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 TTL 7411 74LS10 pin configuration 7411 pin configuration 74LS11 function table 74ls 7410 pin configuration
    Text: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products • Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns


    OCR Scan     		PDF 74LS10 74S10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N TTL 7410 ua 7411 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 TTL 7411 74LS10 pin configuration 7411 pin configuration 74LS11 function table 74ls 7410 pin configuration

    IC 74107

    Abstract: IC 74LS107 74LS107 LS107
    Text: Signelics 74107, LS107 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION transferred to the slave on the H IG H -toLO W Clock transition. For these devices TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74107 20MHz 20mA 74LS107 45MHz


    OCR Scan     		PDF LS107 1N916, 1N3064, 500ns 500ns IC 74107 IC 74LS107 74LS107 LS107

    Untitled

    Abstract: No abstract text available
    Text: M M O TO R O LA SN54/74LS109A D E S C R IP T IO N — The S N 5 4 L S /7 4 L S 10 9 A consists o f tw o high speed com pletely independent tra n sitio n clocked JK flip-flops. The clocking operation is independent of rise and fa ll tim es o f th e d o c k w aveform . The


    OCR Scan     		PDF SN54/74LS109A

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS107 A DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS WITH CLEAR,AND COMPLEMENTARY OUTPUTS Features • Negative edge-triggering • Independent input/output terminals for each flip-flop. • Direct reset input • Q and 5 outputs Pin C o n fig u ra tio n


    OCR Scan     		PDF GD54/74LS107 GD54/74LS107A

    74LS107n

    Abstract: 74107PC IC 74LS107
    Text: 107 CONNECTION DIAGRAM P IN O U T A oft 54/74107 O ' 54LS/74LS107^ n o r D UAL JK FLIP-FLO P With Separate Clears and Clocks Ji ^ DESCRIPTION— T he '107 dual J K master/slave flip-flops have a separate clo ck for each flip-flop. Inputs to the master section are controlled by the


    OCR Scan     		PDF 54LS/74LS107^ 54/74LS CLS107) 74LS107n 74107PC IC 74LS107

    pin diagram of 74109

    Abstract: 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A
    Text: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74109 33MHz 9mA 74LS109A 33MHz 4mA DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K,


    OCR Scan     		PDF LS109A 1N916, 1N3064, 500ns pin diagram of 74109 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A

    Untitled

    Abstract: No abstract text available
    Text: 107 AVG Semiconductors_ DDiT Technical Data DV74LS107A DV74ALS107 Dual JK Negative Edge-Triggered Flip-Flop N Suffix Plastic DIP AVG-001Case The 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initialized by the HIGH-toLOW transition of the clock. A LOW signal on Clear input overrides the


    OCR Scan     		PDF DV74LS107A DV74ALS107 AVG-001Case 74LS107A AVG-002 1-800-AVG-SEMI DV74LS107A, LS107A ALS107

    74ls107a

    Abstract: 74ls107 DV74ALS107
    Text: DDiT Semiconductors Technical Data DV74LS107A DV74ALS107 Dual JK Negative Edge-Triggered Flip-Flop N Suffix Plastic DIP AVG-001Case The 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initialized by the HIGH-toLOW transition of the clock. A LOW signal on Clear input overrides the


    OCR Scan     		PDF 74LS107A DV74LS107 DV74ALS107 AVG-001 AVG-002 500i2 1-800-AVG-SEMI DV74LS107A, DV74ALS107 O1011a 74ls107

    74LS10 pin configuration

    Abstract: No abstract text available
    Text: GD54/74LS10 TRIPLE 3-INPUT POSITIVE NAND GATES Description Pin Configuration This device contains three independent 3-input NAND gates. It performs the Boolean functions Y = A B C or Y = Â + B + Ü in positive logic. Vcc 1C 1Y 3C 3B 3A 3Y 14 13 12 11 10 9


    OCR Scan     		PDF GD54/74LS10 74LS10 pin configuration

    Untitled

    Abstract: No abstract text available
    Text: H D 74LS109A . •REC O M M EN D ED OPERATING Symbol Item /„O 'k Clock frequency Clock High P u lse width Sr.*.v* low “H "D ata Setup tim e “ L 'D a ta th Hold tim e Note 11 The arrow indicates the rising edge. Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear)


    OCR Scan     		PDF 74LS109A T-90-10 74LSOO ib203

    M74LS10P

    Abstract: mitsubishi air conditioning 20-PIN 74LS10P
    Text: MITSUBISHI LSTTLs M 74LS10P T R IP L E 3 -IN P U T P O S IT IV E NAND GATES DESCRIPTION The M 74LS 10P is a semiconductor integrated circuit containing three triple-input positive N A N D and negative N O R gates. FEATURES • High breakdown input voltage V | ^ 15 V


    OCR Scan     		PDF M74LS10P b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN M74LS10P mitsubishi air conditioning 74LS10P

    74LS10P

    Abstract: M74LS10P
    Text: M IT S U B IS H I L S T T L s M 74LS10P TRIPLE 3-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 10P is a semiconductor integrated circuit containing three triple-input positive N A N D and negative N O R gates. FEATURES • High breakdown input voltage V | ^ 15 V


    OCR Scan     		PDF 74LS10P 500ns, b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS10P M74LS10P

    RS flip flop IC

    Abstract: M74LS109AP T flip flop pin configuration Toggle flip flop IC JK flip flop IC 20-PIN toggle type flip flop ic
    Text: MITSUBISHI LSTTLs M 74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLO P WITH S E T AND R ESE T DESCRIPTION PIN C O NFIG URATIO N TOP V IEW The M74LS109AP is a semiconductor integrated circuit containing 2 J-K positive edge-triggered flip-flop circuits


    OCR Scan     		PDF M74LS109AP M74LS109AP 16-PIN 20-PIN RS flip flop IC T flip flop pin configuration Toggle flip flop IC JK flip flop IC toggle type flip flop ic

    74LS109AP

    Abstract: M74LS109 flip flop RS M74LS109AP
    Text: MITSUBISHI LSTTLs M 74LS109A P DUAL J-K P O S IT IV E EDGE-TRIGGERED F L IP FLOP W IT H SET AND RESET DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS109AP is a semiconductor integrated circu it containing 2 J-K positive edge-triggered flip -flo p circuits


    OCR Scan     		PDF 74LS109A M74LS109AP b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS109AP M74LS109 flip flop RS

    74LS107AP

    Abstract: 74LS107* pin and application
    Text: MITSUBISHI LSTTLs M74LS107AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS WITH RESET DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74LS107AP is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T, J and K inputs


    OCR Scan     		PDF M74LS107AP 74LS107AP b2LHfl27 0013Sbl 74LS107* pin and application

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA TC74HC109AP/AF/AFN Dual J-R Flip-Flop with Preset and Clear The TC74HC109A is a high speed CMOS DUAL J-FTFUPFLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.


    OCR Scan     		PDF TC74HC109AP/AF/AFN TC74HC109A 63MHz TC74HC/HCT