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    A63A

    Abstract: 74LSOO
    Text: •Quadruple 2-input Positive AND Gates with Open Collector Outputs IP IN ARRANGEMENT ¡C IR C U IT S C H E M A T IC ^ ) •RECOM M ENDED OPERATING CONDITIONS Symbol min typ max High level output voltage Item VOH - - 5.5 Unit V Low level output current IOL


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    DIVIDE-BY-256

    Abstract: ONU block diagram 74LSOO HD74LS393 a63a
    Text: •D u a l 4-bit Binary Counters This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement tw o individual four-bit counters. The HD74LS393 comprises tw o independent four-bit binary counters each having a clear and a clock input.


    OCR Scan     		PDF HD74LS393 divide-by-256. QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 DIVIDE-BY-256 ONU block diagram 74LSOO a63a

    74LSOO

    Abstract: HD74LS490
    Text: HD74LS490. This c irc u it d itio n a l contains gating to eigh t master-slave im p le m e n t tw o Dual 4 -b it Decade Counters flip -flo p s ind ividu al 4 -b it and ad ­ I BLOCK DIAGRAM K decade counters. Each decade c o u n te r has ind ividu al clo ck, clear, and


    OCR Scan     		PDF HD74LS490. divide-by-100 QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO HD74LS490

    74LSOO

    Abstract: HD74LS642 Hitachi Scans-001
    Text: ♦ O c ta l Bus Transceivers inverted open-collector outputs This octal bus transceiver is designed fo r asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus de­ pending upon the level at the direction control (D IR ) input. The


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    74LSOO

    Abstract: No abstract text available
    Text: •Quadruple 2-input Positive NAND Gates with Open Collector Outputs •C IR C U IT S C H E M A T IC ^ ) BPIN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Symbol min typ max High level output voltage y oh - - 5 .5 Low level output c u rre n t IO L - -


    OCR Scan     		PDF 25ial QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO

    74LSOO

    Abstract: CI 2210 HD74LSoop
    Text: •T rip le 3-input Positive NOR Gates • C IR C U IT S C H E M A T IC ^ B P IN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 2 0 - +75°C ) Item S ym bol T e s t C o n d itio n s min typ* m ax V lH 2 .0 - - V lL - - 0 .8 U n it Input v o lta g e V


    OCR Scan     		PDF -400M 75ial QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO CI 2210 HD74LSoop

    74LSOO

    Abstract: 1S2074
    Text: •Q u a d ru p le 2-input Positive N AND Schmitt-triggers •C IR C U IT S C H EM A TIC ^ HPIN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 20- + 75”C ) Item Symbol min typ* max Unit Vt + V cc — 5V T e s t Conditions 1.4 1.6 1.9 V Vt ~ V cc — 5V


    OCR Scan     		PDF -400M, QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO 1S2074

    74LSOO

    Abstract: HD74LS367A kl66
    Text: HD74LS367A * Hex Bus Drivers non-inverted data outputs with three-state outputs I PIN ARRANGEMENT I CIRCUIT SCHEMATIC D r i v e r se c tio n (1 / 6 ) C o n t r o l se c tio n Ootpu Control Ci ~ï7 ]vVcc — 1Output Cont roi Ci 'vLLKy L jc t-E I 6 " Y r]D *


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    ATML U 010

    Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
    Text: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H D74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM


    OCR Scan     		PDF HD74LS139 QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 ATML U 010 ATML H 010 1S2074 400M 74LSOO OG-16 L400M ATML 010

    Untitled

    Abstract: No abstract text available
    Text: •Quadruple 2-input High-voltage Interface Positive NAND Gates • C IR C U IT SC H EM A TIC O ^ B P IN ARRANGEMENT ■RECOM M ENDED OPERATING CONDITIONS Item S ym bol High lev e l o u tp u t v o lta g e Voh L ow lev el o u tp u t c u r r e n t min ty p


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    Untitled

    Abstract: No abstract text available
    Text: •D u a l 4-input Positive AND Gates •PIN ARRANGEMENT ICIRCUIT SCHEMATICO^ ■ELECTRICAL CHARACTERISTICS Item Input voltage O utput voltage Symbol VlH VlL VOH V>L I ih It L ¡1 Input c u rren t S h o rt-c irc u it output c u rren t Supply c u rren t Input clam p voltage


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    74LSOO

    Abstract: HD74LS374 HD74LSoop
    Text: HD74LS374 • O c t a l D-type Edge-triggered Flip-Flops with th ree-state IP IN ARRANGEM ENT The H D74LS374, 8-bit registers features totem-pole threestate outputs designed specifically for driving highly-capacitive or relatively iow-impedance loads. The high-impedance third


    OCR Scan     		PDF HD74LS374, QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 81mlx 74LSOO HD74LS374 HD74LSoop

    HD74LSoop

    Abstract: 74LSOO 400M HD74LS54 Hitachi Scans-001
    Text: •4 -w id e 2-input, 3-input AND-OR-INVERT Gates • C IR C U IT SCHEM ATIC B P IN ARRANGEMENT N ote The schem atic w ith in the dashed line is included the half inp ut term inals o f H D 7 4 L S 5 4 . ■ELECTRICAL CHARACTERISTICS T a = - 20- + 75°C )


    OCR Scan     		PDF HD74LS54. QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 HD74LSoop 74LSOO 400M HD74LS54 Hitachi Scans-001

    74LSOOP

    Abstract: 74LSOO
    Text: HD74LS21 •D u al 4-input Positive AND Gates •PIN ARRANGEMENT ¡CIRCU IT SCHEMATICO^ ■ ELECTRICAL CH A RA CTERISTICS Item Symbol Input voltage VlL I6i IlH Input current IlL ¡1 Short-circuit output current Supply current Input clamp voltage * T est Conditions


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    HD74LSoop

    Abstract: 74LSOO
    Text: •D u a l 4-input Positive NAND Gates with Open Collector Outputs •C IR C U IT S C H E M A T IC ^ ) « P IN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Item High level output voltage Low leve) output current Symbol min - VoH ÌO L ■ELECTRICAL CHARACTERISTICS (


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    MH1SS1

    Abstract: TESLA mh 7400 MH 7404 mh 7400 tesla cdb 838 tda 7851 L 741PC TDB0124DP tda 4100 TDA 7851 A
    Text: m ö lk ^ o e le l-c te n a n il-c Information Applikation RGW Typenübersicht Vergleich Teil 2: RGW M iM U Z A U l KÉD lnrüÖC=SraO Information Applikation HEFT 50 RGW Typenübersicht + Vergleich Teil 2: RGW wob Halbleiterwerk Frankfurt /oder bt r iab im v«b kombinat mikrootektronik


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    HD74LSoop

    Abstract: No abstract text available
    Text: H D 74L S 164 • 8 - B it Parallel-Out Serial-ln Shift Registers IP IN ARRANGEMENT This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs A and B permit complete control over incoming data as a low at either (or


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    D74LS175

    Abstract: 74LS174 example S174H HD74LSoop 74ls175
    Text: H D 74LS174/H D74LS175 •H e x Quadrupte D-type Rip-Hops with clear IBLOCK DIAGRAM These positive-edge-triggered flip-flops utilize T T L circuitry to implement D-type flip-flop logic. A ll have a direct clear input, and the H D74LS175 features complementary outputs


    OCR Scan     		PDF HD74LS174 HD74LS175 D74LS175 T-90-10 74LSOO ib203 74LS174 example S174H HD74LSoop 74ls175

    Untitled

    Abstract: No abstract text available
    Text: •Q uad ru ple 2-input Exclusive-OR Gates •FU N C TIO N TABLE ■ P IN ARRANGEMENT O u tp u t In p u ts A B Y L L L L H H H L H H H L H ; high level, L ; low level ■ELECTRICAL CHARACTERISTICS Ta= - 2 0 - + 75°C Item S ym bol T e s t C o n d itio n s


    OCR Scan     		PDF T-90-10 ib203

    Untitled

    Abstract: No abstract text available
    Text: H D 74LS 27 •T rip le 3-input Positive NOR Gates IP IN ARRANGEMENT IC IR C U IT S C H E M A T IC H •ELECTRICAL CHARACTERISTICS Ta= - 2 0 - +75°C ) Item Symbol T e s t C onditions min typ* max V lH 2 .0 - - V lL - - 0 .8 Unit Input voltage V VOH Vcc = 4 . 7 5 V , V / ¿ = 0 . 8 V . f o w = - 4 0 0 / í A


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    hd74lsoop

    Abstract: No abstract text available
    Text: H D 74L S 126A ICIRCUIT SCHEMATIC •Quadruple Bus Buffer Gates with three-state outputs (%) IPIN ARRANGEMENT •FUNCTION TABLE Inputs C L H H Outputs Y Z H L A X H L Note) H; high level, L; low level, X; irrelevant Z; off (high-im pedance) gute of a 3 *«tate output


    OCR Scan     		PDF HD74LS126A T-90-10 74LSOO ib203 hd74lsoop

    Untitled

    Abstract: No abstract text available
    Text: • 8 -Nne-to-3-line Octal Priority Encoders IBLOCK DIAGRAM The H D 74LS148 encodes eight data lines to three-line 4-2-1 binary (octal). Cascading circuitry (enable input El and enable output EO) has been provided to allow octal expansion w ith ­ out the need for external circuitry. The data inputs and out­


    OCR Scan     		PDF 74LS148 T-90-10 74LSOO ib203

    D74LS

    Abstract: D74LS08
    Text: H D 74LS 08 •Quadruple 2-input Positive AND Gates •PIN ARRANGEMENT ¡CIRCUIT S C H E M A T IC ^ ■ELECTRICAL CHARACTERISTICS T a = - 2 0 ~ +75"C ) Item Input voltage Symbol Test Conditions min - V lL - - 0 .8 V 2.7 - - V - - 0.5 - - - - V cc = 4.75V ,


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    Untitled

    Abstract: No abstract text available
    Text: • 8 - b i t Addressable Latches This 8*bit addressable latch is designed for general purpose storage applications in digital systems. Specific uses include w orking registers, serial-holding registers, and active-high de­ coders or demultiplexers. This is multifunctional device capa­


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