MT4C4001
Abstract: mt4c4001jdc sm03b
Text: MICRON TECHNOLOGY INC 55E D WÊ blllSHT ITT H I URN M T4C4001J DIE 1 MEG x 4 DRAM fAICRQN MILITARY DRAM DIE 1 MEG x 4 DRAM DIE FEATURES DIE OUTLINE Top View 14 13 12 11 10 15 5 4 3 2 □ □ □ □ □ □□□ □ □ □ □□□ □ DIE DATA BASE D15B
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OCR Scan
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T4C4001J
450mW
024-cycle
MT4C4001
mt4c4001jdc
sm03b
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PDF
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Untitled
Abstract: No abstract text available
Text: M T4C4003J lEG X 4 DRAM M IC R O N 1 MEG DRAM X 4 DRAM DRAM STATIC COLUMN FEATURES PIN ASSIGNMENT (Top View OPTIONS 20-Pin ZIP (DC-1) (DB-2) DQ1 DQ2 WE RAS A9 MARKING • Timing 70ns access 80ns access • Packages Plastic SOJ (300 mil) Plastic ZIP (350 mil)
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OCR Scan
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T4C4003J
024-cycle
20/26-Pin
20-Pin
MT4C4003J
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PDF
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T4C400
Abstract: mt4c4004jdj
Text: M T4C4004J 1 MEG X 4 DRAM l^ldRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST PAGE MODE FEATURES _ • Four independent C A S controls, allo w ing in d ivid u al m anipulation to each of the four data In p u t/O u tp ut ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words w hen using 1 M eg x 4 D R A M s for m emory
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OCR Scan
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T4C4004J
36bit
225mW
024-cycle
MT4C4001JDJ
MT4C4004JDJ
MT4C4004J
MT4C40040
T4C400
mt4c4004jdj
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PDF
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T4C4001JDJ-6
Abstract: mt4c4001
Text: T4C4001 J S 1 MEG X 4 DRAM [M IC R O N DRAM 1 MEG X 4 DRAM FEATURES • 1,024-cycle refresh distributed across 16ms (T4C4001J) or 128ms (M T4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM O S silicon-gate process
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OCR Scan
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MT4C4001
024-cycle
MT4C4001J)
128ms
T4C4001J
MT4C4001J
225mW
20/26-Pin
20-Pin
T4C4001JDJ-6
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE M IC R O N M T4C40004/5 4 MEG x 4 DRAM FAST PAGE MODE: T4C40004 STATIC COLUMN: T4C40005 FEATURES • Industry standard x4 pinout, timing, functions and packages • High performance, CMOS silicon gate process • Single power supply : +5V±10% or +3.3V±10%
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OCR Scan
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T4C40004/5
250mW
2048-cycle
4096-cycle
475mil)
400mil)
MT4C40004/5
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PDF
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Untitled
Abstract: No abstract text available
Text: M T 4 C 4 0 0 1 J S 1 MEG x 4 DRAM |U|(=RON DRAM 1 MEG x 4 DRAM 5V, STANDARD OR SELF REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (M T4C4001J) or 128ms (M T4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM OS silicon-gate process
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OCR Scan
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024-cycle
T4C4001J)
128ms
T4C4001J
MT4C4001J
20/26-Pin
MT4C4001
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PDF
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intel 29F
Abstract: T7164 28F Intel LV6416 4c4007 5B810 32kxS 62832 dram cross reference T5C2568
Text: A Fast SRAM cross reference Vendor Cypress Hitachi Code ASCCode Description Code ASC Code CY 7C 185 A S7C 164 81x8 M C M 6264C AS7C164 8Kx8 CY 7C 199 A 57C 256 32K x8 M C M 6206D A S7C2S6 32K x8 C Y 7 C J3 9 9 A S7C 32S6 3 2 K * 8 3V M CM 62V06D A S7C 3256
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OCR Scan
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628127H
T7164
712S6
DT71Q08
1S61C64AH
LS61C2S6AH
IS61LV3216
S61C512
IS61C64
S61LV256
intel 29F
T7164
28F Intel
LV6416
4c4007
5B810
32kxS
62832
dram cross reference
T5C2568
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PDF
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Untitled
Abstract: No abstract text available
Text: 1, 2 MEG X 32 DRAM SIMMs MICRON • ItCHtfULOGYIMC D R A M L ^ r iA A lV I MT8D132 X MT16D232(X) MODULE FEATURES PIN ASSIGNMENT (Front View) • JEDEC- and industry-standard pinout in a 72-pin, single in-line m emory module (SIMM) • 4M B (1 M eg x 32) and 8MB (2 M eg x 32)
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OCR Scan
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MT8D132
MT16D232
72-pin,
024-cycle
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PDF
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY .ü ïïi04,0^ !? -j, MEG x 4 DRAM « ch«oL„ „ « DRAM 1 MEG x 4 DRAM FEATURES * * » * «• Single +5V ±10% power supply JEDEC-standard pinout and packages High-perform ance CMOS silicon-gate process All inputs, outputs and clocks are TTL-com patible
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OCR Scan
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024-cycle
128ms
25-35ns
128ms
MT4C4007J
001E024
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PDF
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T4C4001JDJ-6
Abstract: T4C4001
Text: DRAM 1 MEG X 4 DRAM LOW POWER, EXTENDED REFRESH FEATURES • Industry standard x4 pinout, tim ing, functions and packages • High-performance, CM OS silicon-gate process • Single +5V ±10% power supply • All inputs, outputs and clocks are fully TTL compatible
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OCR Scan
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T4C4001J
024-cycle
128ms
225mW
20-Pin
MT4C4001JL
T4C4001JDJ-6
T4C4001
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PDF
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MT4C4001
Abstract: No abstract text available
Text: MT20D240 2 MEG X 40 DRAM M ODULE p iC R O fS J 2 MEG X 40 DRAM DRAM MODULE NEW I FAST PAGE MODE MT20D240 LOW POWER, EXTENDED REFRESH (MT20D240 L) FEATURES • • • • PIN ASSIGNMENT (Top View) 72-pin single-in-line package High-performance CM OS silicon-gate process.
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OCR Scan
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MT20D240
72-pin
024-cycle
128ms
MT20D240)
MT4C4001
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PDF
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MT4C4007JDJ
Abstract: ST bsx 26
Text: MTHat3Z XI(SFr MTt6D222(XJ (S | t M B G *ZM EE jc3ZDRÄIW1 M O D ULE DRAM 1 MEG, 2 MEG x 32 M UW D U L tr - 4, 8 MEGABYTE, 5V, OPTIONAL SELF REFRESH, FAST PAGE OR EDO PAGE MOPE FEATURES • JE D E C - a n d i n d u s tr y - s ta n d a r d pinout in a 72-pin,
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OCR Scan
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MTt6D222
72-pin,
23ZIX
MT4C4007JDJ
ST bsx 26
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PDF
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W9C 08
Abstract: marking W9C MT4C400
Text: SSE D MICRON TECHNOLOGY INC blllSMT □ 0 G S 7 M C1 3T7 M N R N T4C4001J 883C 1 MEG X 4 DRAM IC Z R O N MILITARY DRAM 1 MEG X 4 DRAM FAST PAGE MODE PIN ASSIGNMENT Top View • SMD 5962-90847, Class M • JAN 5962-90847, Class B • MIL-STD-883, Class B
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OCR Scan
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MT4C4001J
MIL-STD-883,
20-Pin
450mW
024-cycle
MIL-STO-883
W9C 08
marking W9C
MT4C400
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PDF
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Untitled
Abstract: No abstract text available
Text: MICR ON S E M I C O N D U C T O R INC b3E D • b l l l S M T D D D V bb ? 51b ■ MRN T4C4004J 1 MEG x 4 DRAM I^HCRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST-PAGE-MODE FEATURES _ PIN ASSIGNMENT Top View • Four independent CAS controls, allowing individual
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OCR Scan
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MT4C4004J
36bit
275mW
A1993,
T4C4001JDJ
T4C4004JDJ
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PDF
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Untitled
Abstract: No abstract text available
Text: T4C4001 J S 1 MEG X 4 DRAM (MICRON DRAM 1 MEG x 4 DRAM 5V, STANDARD OR SELF REFRESH • 1,024-cycle refresh distributed across 16ms (T4C4001J) or 128ms (T4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM OS silicon-gate process
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OCR Scan
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MT4C4001
024-cycle
MT4C4001J)
128ms
MT4C4001J
20/26-Pin
001217T
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PDF
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Untitled
Abstract: No abstract text available
Text: M IC R O N I T4C4003J 1 MEG X 4 DRAM 1 MEG X 4 DRAM DRAM STATIC COLUMN FEATURES PIN ASSIGNMENT Top View • Industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single +5V ±10% power supply • Low power, 3mW standby; 225m W active, typical
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OCR Scan
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MT4C4003J
024-cycle
20/26-Pin
T4C4003JDJ-7
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PDF
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pin diagram for IC 7476
Abstract: INTERNAL DIAGRAM OF IC 7476
Text: ADVANCE |U|ICRON 1 MEG 1 MEG DRAM MODULE MT16D T 164 64 DRAM MODULE 64 DRAM FAST PAGE MODE (MT16D(T)164) LOW POWER, EXTENDED REFRESH (MT16D(T)164 L) FEATURES PIN A SSIG N M E N T (Top View) • Industry-standard pinout in a 168-pin, dual read-out, single in-line package
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OCR Scan
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MT16D
168-pin,
600mW
024-cycle
128ms
168-Pi
pin diagram for IC 7476
INTERNAL DIAGRAM OF IC 7476
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PDF
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marking wml
Abstract: j-l003 marking WMM C1994 MT4C4001 MT4C4001J MT4C4001JDJ-6
Text: M ir n O M I .“ hT M T 4C 4001J S 1 M EG X 4 D R A M 1 MEG DRAM X 4 DRAM STANDARD OR SELF REFRESH a J3 > FEATURES • 1,024-cycle refresh distributed across 16ms (T4C4001J) or 128ms (T4C4001J S) • Industry-standard pinout, timing, functions and packages
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OCR Scan
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MT4C4001
024-cycle
MT4C4001J)
128ms
MT4C4001J
225mW
CI994.
marking wml
j-l003
marking WMM
C1994
MT4C4001JDJ-6
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PDF
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LIS-1024
Abstract: No abstract text available
Text: OBSOLETE M I C R O N 1 ^cnllvZ DRAM E G x 4 T4C4007J FEATURES PIN ASSIGNMENT Top View • • • • • Single +5V +10% pow er supply JED EC-standard pinout and packages H igh-perform ance CM OS silicon-gate process All inputs, outputs and clocks are TTL-com patible
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OCR Scan
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024-cycle
128ms
MT4C4007J
20/26-Pin
128ms
LIS-1024
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PDF
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Untitled
Abstract: No abstract text available
Text: [m i c r o T4C4003J 1 MEG X 4 DRAM n DRAM 1 MEG X 4 DRAM STATIC COLUMN FEATURES • Industry standard x4 pinout, timing, functions and packages • High-performance, C M O S silicon-gate process • Single +5V ±10% p ow er supply • L o w power, 3 m W standby; 225mW active, typical
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OCR Scan
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MT4C4003J
225mW
024-cycle
20-Pin
70nsde
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PDF
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T4C4004JDJ
Abstract: marking W7F
Text: T4C4004J 1 MEG X 4 DRAM I^ IIC R O N DRAM 1 MEG x 4 DRAM FEATURES _ PIN ASSIGNMENT Top View • Four independent CAS controls, allowing individual manipulation to each of the four data inpu t/output ports (DQ1 through DQ4). • Offers a single chip solution to byte level parity for 36bit words when using 1 M eg x 4 DRAMs for memory
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OCR Scan
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MT4C4004J
36bit
275mW
024-cycle
24-Pin
MT4C4001JDJ
MT4C4004JDJ
T4C4004JDJ
marking W7F
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PDF
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T4C4007JDJ-7
Abstract: No abstract text available
Text: PRELIMINARY T4C4007J S 1 MEG X 4 DRAM M IC R O N 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL SELF REFRESH FEATURES PIN ASSIGNMENT (Top View) • • • • • Single +5V ±10% power supply JEDEC-standard pinout and packages High-perform ance CM OS silicon-gate process
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OCR Scan
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MT4C4007J
024-cycle
128ms
25-35ns
20/26-Pin
T4C4007JDJ-7
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PDF
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U15-U10
Abstract: MT18D236
Text: MT9D136, MT18D236 1 MEG. 2 MEG x 36 DRAM MODULE |V /|ICZRO N DRAM MODULE 1 MEG, 2 MEG x 36 FEATURES PIN ASSIGNMENT Front View • C o m m o n R A S co n tro l p er sid e p in o u t in a 72-p in , sin g le-in -lin e m em o ry m o d u le (SIM M ) • H ig h -p e rfo rm a n ce C M O S silico n -g a te p ro cess.
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OCR Scan
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MT9D136,
MT18D236
72-Pin
MT1BD236
U15-U10
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PDF
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T4C4007J
Abstract: No abstract text available
Text: OBSOLETE 1, 2 MEG X 32 DRAM SIMMs MICRON I TECHNOLOGY, INC. MT8D132 X MT16D232(X) DRAM MODULE FEATURES PIN ASSIGNMENT (Front View) • JED EC - and industry-standard pinout in a 72-pin, single in-line m em ory m odule (SIMM) • 4M B (1 M eg x 32) and 8MB (2 M eg x 32)
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OCR Scan
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MT8D132
MT16D232
72-pin,
024-cycle
72-Pin
T4C4007J
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PDF
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