Contextual Info: |U |IC=RO N 2 MEG DRAM MODULE X MT18D236 36 DRAM MODULE 2 MEG x 36 DRAM FAST PAGE MODE FEATURES • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance, CMOS silicon-gate process. • Single 5V ±10% power supply • All device pins are fully TTL compatible

MT18D236

Contextual Info: |U|K=RON 2 MEG DRAM MODULE 2 MEG X MT18D236 36 DRAM MODULE X 36 DRAM FAST-PAGE-MODE FEATURES • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance CMOS silicon-gate process. • Single 5V ±10% power supply • All device pins are TTL-compatible

MT18D236

Contextual Info: [MICRON 2 MEG DRAM MODULE X MT18D236 36 DRAM MODULE 2 MEG X 36 DRAM FAST-PAGE-MODE FEATURES PIN A SSIG N M EN T Top View • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance CM OS silicon-gate process. • Single 5V ±10% power supply

Contextual Info: MICRON S E M I C O N D U C T O R INC b3E J> b l l l S M T OOGfllHS T3fl • MRN m l^ iic n o N 2 MEG DRAM MODULE X MT18D236 36 DRAM MODULE 2 MEG x 36 DRAM FAST-PAGE-MODE FEATURES PIN ASSIGNMENT Top View • Comm on RA S control per side pinout in a 72-pin

MT18D236G6

Contextual Info: l^ iic n o N 2 MEG X MT18D236 36 DRAM MODULE 2 MEG X 36 DRAM DRAM MODULE FAST PAGE MODE FEATURES • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance, CM OS silicon-gate process. • Single 5V ±10% power supply • All device pins are fully TTL compatible

U15-U10

Abstract: MT18D236
Contextual Info: MT9D136, MT18D236 1 MEG. 2 MEG x 36 DRAM MODULE |V /|ICZRO N DRAM MODULE 1 MEG, 2 MEG x 36 FEATURES PIN ASSIGNMENT Front View • C o m m o n R A S co n tro l p er sid e p in o u t in a 72-p in , sin g le-in -lin e m em o ry m o d u le (SIM M ) • H ig h -p e rfo rm a n ce C M O S silico n -g a te p ro cess.

MT4C4007JDJ

Contextual Info: ADVANCE MICRON MT9D136A X, MT18D236A X 1 MEG, 2 MEG x 36 DRAM MODULES DRAM MODULE 1 MEG, 2 MEG x 36 • TECHNOLOGY, INC. 4, 8 MEGABYTE, 5V, ECC, EDO PAGE MODE FEATURES • Four CAS# ECC pinout in a 72-pin, single-in-line memory module SIMM • High-performance CMOS silicon-gate process

Contextual Info: R /lin S n M I ii^ n w r « MT9D136; W1T18D236 t MEGr 2 MEG x 36 DRAM MODULE 1 MEG, 2 MEG X 36 DRAM MODULE FAST PAGE MODE FEATURES • Common RAS control per side pinout in a 72-pin, single-in-line memory module • High-performance CMOS silicon-gate process.

MT18D236

Contextual Info: DRAM MODULE 1 MEG, 2 MEG x 36 4, 8 MEGABYTE, 5V 4 ,8ME GABY TE’5VFAST PAGE MODE FEATURES PIN ASSIGNMENT Front View • Common RAS control per side pinout in a 72-pin, single-in-line m emory module (SIMM) • High-performance CM OS silicon-gate process.

MT4C4001d

Abstract: MT4C4001DJ dram 72-pin simm micron 32
Contextual Info: ÛOQSMbS 1 MÊtlRN ADVANCE .in,-;."M~1'.lu1.il".,1,.J.rM*1. ^ J W 1 T -M -zz-n 2 MEG X 36 DRAM DRAM MODULE FAST PAGE MODE PIN ASSIGNMENT Top View • Common RAS control per side pinout in a 72-pin single-in-line package • High-performance CMOS silicon gate process.

MT4C4007JDJ

Contextual Info: ADVANCE M T 9 D 1 3 6 A X, M T 1 8 D 2 3 6 A X 1 MEG, 2 MEG x 36 DR AM M O D U L E S DRAM MODULE 1 MEG, 2 MEG x 36 4, 8 MEGABYTE, 5V, ECC, EDO PAGE MODE FEATURES * * * * * * * * PIN ASSIGNMENT Front View Four CAS# ECC p in o u t in a 72-pin, single-in-line