Untitled
Abstract: No abstract text available
Text: Zener Diodes 1W Type No. Device Marking Code PL3V6C PL3V9C PL4V3C PL4V7C PL5V1C PL5V6C PL6V2C PL6V8C PL7V5C PL8V2C PL9V1C PL10C PL11C PL12C PL13C PL15C PL16C PL18C PL20C PL22C PL24C PL27C PL30C PL33C PL36C PL39C PL43C PL47C PL51C PL56C PL62C PL68C PL75C PL82C
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PL10C
PL11C
PL12C
PL13C
PL15C
PL16C
PL18C
PL20C
PL22C
PL24C
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pt45
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
110mW
VCC12.
LFSC25
900-Ball
pt45
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.4b, February 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
SC115
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 01.6, August 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
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PDF
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81c78
Abstract: 7C291 5962-8515505RX 27PC256-12 PAL164A 8464C 5C6408 72018 39C10B MACH110 cross reference
Text: Product Line Cross Reference CYPRESS 2147-35C 2147-45C 2147-45C 2147-45M+ 2147-55C 2147-55M 2148-35C 2148-35C 2148-35M 2148-45C 2148-45C 2148-45M 2148-45M+ 2148-55C 2148-55C 2148-55M 2149-35C 2149-35C 2149-35M 2149-45C 2149-45M 2149-45M 2149-55C 2149-55C 2149-55M
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Original
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2147-35C
2147-45C
2147-45M+
2147-55C
2147-55M
2148-35C
2148-35M
2148-45C
81c78
7C291
5962-8515505RX
27PC256-12
PAL164A
8464C
5C6408
72018
39C10B
MACH110 cross reference
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PDF
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2-bit comparator
Abstract: LFSC3GA15E-5F900I PR77A PR55D pr94a diode transistor pt36c pt36C PB110C pb127d PB138
Text: LatticeSC/M Family Data Sheet DS1004 Version 01.8, November 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
2-bit comparator
LFSC3GA15E-5F900I
PR77A
PR55D
pr94a diode
transistor pt36c
pt36C
PB110C
pb127d
PB138
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
LFSC25
FF1020
LFSC80
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PDF
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PB68C
Abstract: LFSCM3GA40EP1
Text: LatticeSC Family Data Sheet DS1004 Version 01.4a, January 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
LVPECL33
SC115
PB68C
LFSCM3GA40EP1
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.3, August 2006 LatticeSC Family Data Sheet Introduction August 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
110mW
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PDF
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pb127d
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.2, December 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
pb127d
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 01.9, January 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.0, March 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os
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Original
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DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
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PDF
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PB110C
Abstract: PB124A pt36C SCM15 BA5 904 AF P PL80B PR55D pr94a diode transistor pt36c transistor pt42c
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features – 1 to 7.8 Mbits memory – True Dual Port/Pseudo Dual Port/Single Port – Dedicated FIFO logic for all block RAM
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Original
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DS1004
DS1004
500MHz
700MHz
600Mbps
125Gbps)
1A-10
1152-ball
1704-ball
PB110C
PB124A
pt36C
SCM15
BA5 904 AF P
PL80B
PR55D
pr94a diode
transistor pt36c
transistor pt42c
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PDF
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|
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PB80D
Abstract: PR87A PR98A PR96A PB110C pr94a diode pt36C pr77a transistor pt36c transistor pt42c
Text: LatticeSC/M Family Data Sheet DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features – 1 to 7.8 Mbits memory – True Dual Port/Pseudo Dual Port/Single Port – Dedicated FIFO logic for all block RAM
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Original
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DS1004
DS1004
500MHz
700MHz
600Mbps
125Gbps)
1A-10
1152-ball
1704-ball
PB80D
PR87A
PR98A
PR96A
PB110C
pr94a diode
pt36C
pr77a
transistor pt36c
transistor pt42c
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PDF
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Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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Original
|
DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
LFSC25
FF1020
LFSC80
|
PDF
|
Untitled
Abstract: No abstract text available
Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks
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Original
|
DS1004
DS1004
700MHz
600Mbps
125Gbps)
105mW
LFSC25
FF1020
LFSC80
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PDF
|
Untitled
Abstract: No abstract text available
Text: QL8x12BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 MHz at 3.3 Volt operation. 5Y Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and
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OCR Scan
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QL8x12BL
8-by-12
44-pin
68-pin
100-pin
8x12BL
PL68C
68-pin
PF100
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PDF
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Untitled
Abstract: No abstract text available
Text: QL8X12B W ildCat 1000 Very-High-Speed IK 3K Gate CMOS FPGA Rev A pASIC HIGHLIGHTS Eg Very High Speed - V iaL ink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 M Hz and logic cell delays of under 2 ns. Q High Usable Density - An 8-by-12 array of 96 logic cells provides 3,000
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OCR Scan
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QL8X12B
8-by-12
44pin
68-pin
100-pin
16-bit
44-pin
PF100
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PDF
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Untitled
Abstract: No abstract text available
Text: QL8X12B WildCaX 1000 Very-High-Speed IK 3K Gate CMOS FPGA Rev A B antifuse technology, allow s co u n ter speeds o v er 150 M H z and logic cell delays o f un d er 2 ns. Q .1000 usable gates, 64 I/O pins Very High Speed - V ia L in k m etal-to-m etal p ro g ra m m a b le-v ia
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OCR Scan
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QL8X12B
8-by-12
44pin
68-pin
100-pin
16-bit
Tools2-55,
8X12B-1
PL68C
44-pin
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PDF
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pl68c
Abstract: No abstract text available
Text: QL8x12BL Wildcat 1000L Low Power 3.3 Volt Operation, IK Gate FPGA B .1000 usable gates, 64 I/O pins High Speed - V ia L in k metal-to-metal programmable-via antifuse technology, allows counter speeds over 80 M H z at 3.3 Volt operation. 1 Q pASIC pASIC
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OCR Scan
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QL8x12BL
1000L
8-by-12
44-pin
68-pin
100-pin
8X12BL-1
PL68C
pl68c
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PDF
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pl68c
Abstract: No abstract text available
Text: QL8X12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS S Very High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays o f under 2 ns. .1,000 E High Usable Density - An 8-by-12 array of 96 logic cells provides
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OCR Scan
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QL8X12B
8-by-12
44-pin
68-pin
100-pin
16-bit
QL8X12B-1
PL68C
pl68c
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PDF
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ACT1020
Abstract: QL12X16-1PL68C ACT1020 pga pl68c ACT1020 fpga
Text: bSE D flUICK LOGIC RQD3Q3D 00DQ057 b4T M ü l l I C QL12X16 pASIC 1 FAMILY Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS B Very H igh Speed - ViaLink metal-to-metal progranunable-via anti fuse technology, allows counter speeds over 100 MHz, and logic cell
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OCR Scan
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00DQ057
QL12X16
12-by-16
68-pin
100-pin
16-bit
12x16
ACT1020
QL12X16-1PL68C
ACT1020 pga
pl68c
ACT1020 fpga
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PDF
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QL8X12A
Abstract: pl68c 96
Text: QL8X12A pASIC 1 FAMILY Very-High-Speed IK 3K Gate CMOS FPGA April 1993 pASIC HIGHLIGHTS RSI Very-High-Speed, Flexible FPGA Architecture - ViaLink metal-tometal, low-resistance antifuse (<50 ohm) interconnect technology allows data path performance over 125 MHz with logic cell delays of under 2.5 ns.
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OCR Scan
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QL8X12A
8-by-12
L8X12A
QL8x12A
QU1KS002
pl68c 96
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PDF
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