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    PIN CONFIGURATION 74LS10 Search Results

    PIN CONFIGURATION 74LS10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-DSDMDB09MF-010 Amphenol Cables on Demand Amphenol CS-DSDMDB09MF-010 9-Pin (DB9) Deluxe D-Sub Cable - Copper Shielded - Male / Female 10ft Datasheet
    CS-DSDMDB15MF-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB15MF-002.5 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Female 2.5ft Datasheet
    CS-DSDMDB15MM-025 Amphenol Cables on Demand Amphenol CS-DSDMDB15MM-025 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Male 25ft Datasheet
    CS-DSDMDB25MM-010 Amphenol Cables on Demand Amphenol CS-DSDMDB25MM-010 25-Pin (DB25) Deluxe D-Sub Cable - Copper Shielded - Male / Male 10ft Datasheet
    CS-DSDMDB37MM-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB37MM-002.5 37-Pin (DB37) Deluxe D-Sub Cable - Copper Shielded - Male / Male 2.5ft Datasheet

    PIN CONFIGURATION 74LS10 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    74LS10 pin configuration

    Abstract: No abstract text available
    Text: GD54/74LS10 TRIPLE 3-INPUT POSITIVE NAND GATES Description Pin Configuration This device contains three independent 3-input NAND gates. It performs the Boolean functions Y = A B C or Y = Â + B + Ü in positive logic. Vcc 1C 1Y 3C 3B 3A 3Y 14 13 12 11 10 9


    OCR Scan     		PDF GD54/74LS10 74LS10 pin configuration

    74LS107AP

    Abstract: 74LS107* pin and application
    Text: MITSUBISHI LSTTLs M74LS107AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS WITH RESET DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74LS107AP is a semiconductor integrated circuit containing 2 J-K negative edge-triggered flip -flo p circuits w ith discrete terminals fo r clock input T, J and K inputs


    OCR Scan     		PDF M74LS107AP 74LS107AP b2LHfl27 0013Sbl 74LS107* pin and application

    74LS109AP

    Abstract: M74LS109 flip flop RS M74LS109AP
    Text: MITSUBISHI LSTTLs M 74LS109A P DUAL J-K P O S IT IV E EDGE-TRIGGERED F L IP FLOP W IT H SET AND RESET DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS109AP is a semiconductor integrated circu it containing 2 J-K positive edge-triggered flip -flo p circuits


    OCR Scan     		PDF 74LS109A M74LS109AP b2LHfl27 0013Sbl 14-PIN 16-PIN 20-PIN 74LS109AP M74LS109 flip flop RS

    74ls163 function table

    Abstract: No abstract text available
    Text: GD54/74LS163A SYNCHRONOUS 4-BIT COUNTER: BINARY, SYNCHRONOUS CLEAR Feature • • • • • • Pin Configuration Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Load Control Line Diode-Clamped Inputs


    OCR Scan     		PDF GD54/74LS163A 000424G 74ls163 function table

    M74LS107AP

    Abstract: 74LS107AP M74LS73AP 20-PIN 74ls107a 74LS107* pin and application
    Text: M IT S U B IS H I LSTTLs M74LS107AP DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOPS W ITH RESET DESCRIPTION The PIN CONFIGURATION TOP VIEW M 74LS107A P conta in in g 2 J -K is a sem ico n d u c to r in teg rated c irc u it negative edge-triggered flip -flo p circuits


    OCR Scan     		PDF M74LS107AP M74LS107AP b2LHfl27 0013Sbl 74LS107AP M74LS73AP 20-PIN 74ls107a 74LS107* pin and application

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS109A DUAL POSITIVE-EDGE- TRIGGERED J-K FLIP-FLOPS Feature Pin Configuration • Positive Edge-Triggering • Direct Set and reset inputs • J and K inputs • Q and Q outputs Vcc CLR2 J2 K2 C LK 2 PR2 Q2 QS R RRRFI R HR y Description This device contains two independent positiveedge-triggered J-K flip-flops with complementary out­


    OCR Scan     		PDF GD54/74LS109A

    J-K Flip flops

    Abstract: No abstract text available
    Text: MITSUBISHI HIGH S P E E D CMOS M74HC107P/FP/DP DUAL J-K F L I P - F L O P WITH R E S E T DESCRIPTION The M74HC107 is a semiconductor integrated circuit con­ sisting of two negative-edge triggered J-K flip flops with in­ dependent control inputs PIN CONFIGURATION TOP VIEW


    OCR Scan     		PDF M74HC107P/FP/DP M74HC107 50MHz 10/uW/package, 74LSTTL 14P2P 14-PIN 16P2P 16-PIN 20P2V J-K Flip flops

    74LS10 mitsubishi

    Abstract: No abstract text available
    Text: M IT S U B IS H I HIGH SPEED CMOS M74HC10P/FP/DP T R IP L E 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74HC10 is a semiconductor integrated circuit con­ sisting of three 3-input positive-logic NAND gates, usable as negative-logic NOR gates.


    OCR Scan     		PDF M74HC10P/FP/DP M74HC10 74LSTTL 14P2P 14-PIN 16P2P 16-PIN 20P2V 20-PIN 74LS10 mitsubishi

    Untitled

    Abstract: No abstract text available
    Text: MITSUBISHI HIGH SPEED CMOS M74HC10P M74HC10DP T R IP L E 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION The M 74H C 10 is a sem iconductor integrated c ircu it con­ sisting of three 3-in put p o s itiv e -lo g ic NAND, PIN CONFIGURATION TOP VIEW usable as


    OCR Scan     		PDF M74HC10P M74HC10DP

    pin configuration 74LS10

    Abstract: M74HC10P 4000B 74LS10 M74HC10 M74HC10DP of IC 74ls10 CMOS 74LS10 logic diagram of IC 74ls10 74LS10 mitsubishi
    Text: M IT S U B IS H I HIGH S P E E D C M O S M74HC10P M74HC10DP T R IP L E 3 -IN P U T P O S IT IV E NAND G A TE DESCRIPTION The M 74H C 10 is a sem iconductor integrated circu it con­ sisting of three 3-input p o sitive-lo gic PIN CONFIGURATION TOP VIEW NAND, usable as


    OCR Scan     		PDF M74HC10P M74HC10DP M74HC10 pin configuration 74LS10 4000B 74LS10 M74HC10DP of IC 74ls10 CMOS 74LS10 logic diagram of IC 74ls10 74LS10 mitsubishi

    Untitled

    Abstract: No abstract text available
    Text: MI TSUBI SHI HIGH S P E E D CMOS M74HC109P DUAL J-K F L I P - F L O P WI TH S E T AND R E S E T DESCRIPTION The M 74H C 109 is a sem iconductor integrated c irc u it con­ PIN CONFIGURATION TOP VIEW sisting of tw o po s itiv e -e d g e trig g e re d J -K flip -flo p s w ith in­


    OCR Scan     		PDF M74HC109P

    Untitled

    Abstract: No abstract text available
    Text: M IT SU BISH I HIGH S P E E D CM O S & M74HC107P g v ' V\\'^ ' ste DUAL J-K F L I P - F L O P WITH R E S E T DESCRIPTION T he M 7 4 H C 1 0 7 is a sem ico n d u cto r integrated circuit co n­ PIN CONFIGURATION TOP VIEW sistin g of tw o n e g a tiv e -e d g e trig g ered J - K flip flo p s with in­


    OCR Scan     		PDF M74HC107P

    RS flip flop IC

    Abstract: JK flip flop IC RS flip flop cmos Toggle flip flop IC M74HC109P 4000B 74LS109 M74HC109 RS flip flop
    Text: M IT S U B IS H I HIGH S P E E D C M O S M 74H C 109P D U A L l- K F L IP -F L O P W IT H S E T A ND R E S E T DESCRIPTION The M 74H C 109 is a sem iconductor integrated c irc u it con­ PIN CONFIGURATION TOP VIEW sisting of tw o p o s itiv e -e d g e trig g e re d J -K flip -flo p s w ith in­


    OCR Scan     		PDF M74HC109P M74HC109 50MHz 10/zW/package M74HC10idth RS flip flop IC JK flip flop IC RS flip flop cmos Toggle flip flop IC M74HC109P 4000B 74LS109 RS flip flop

    74HC109P

    Abstract: No abstract text available
    Text: MITSUBISHI HIGH S P E E D CMOS M 74H C 109P /FP /D P DUAL i-K F L I P - F L O P WITH S E T AND R E S E T DESCRIPTION T h e M 7 4 H C 1 0 9 is a s e m ic o n d u c to r in te g r a te d c irc u it c o n ­ PIN CONFIGURATION TOP VIEW s is tin g of tw o p o s it iv e -e d g e t r ig g e r e d J - K flip flo p s w ith in ­


    OCR Scan     		PDF

    Untitled

    Abstract: No abstract text available
    Text: H D 74LS109A . •REC O M M EN D ED OPERATING Symbol Item /„O 'k Clock frequency Clock High P u lse width Sr.*.v* low “H "D ata Setup tim e “ L 'D a ta th Hold tim e Note 11 The arrow indicates the rising edge. Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear)


    OCR Scan     		PDF 74LS109A T-90-10 74LSOO ib203

    74LSOO

    Abstract: 1S2074 HD74LS109A HD74LS109
    Text: H D 74LS109A . Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear IP IN ARRANGEMENT •REC O M M EN D ED OPERATING CONDITIONS S ym bol Item fro c k C lock fre q u e n c y C lo c k High P u ls e w idth Sr.*.v* low “ H " D a ta S e tu p tim e


    OCR Scan     		PDF HD74LS109A. QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO 1S2074 HD74LS109A HD74LS109

    LM 7410

    Abstract: No abstract text available
    Text: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns


    OCR Scan     		PDF 74LS10 74S10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N LM 7410

    TTL 7410

    Abstract: 74LS11 function table 74LS10 pin configuration TTL 7410 AND propagation delay 7411 signetics
    Text: Signetics I 7410, 7411, LS10, LS11 S10, S11 Gates Logic Products • Triple Three-Input NAND '10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S1Û 3ns 12mA 7411 10ns


    OCR Scan     		PDF 74LS10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N N74LS10D, TTL 7410 74LS11 function table 74LS10 pin configuration TTL 7410 AND propagation delay 7411 signetics

    TTL 7411

    Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
    Text: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA


    OCR Scan     		PDF 74LS10 74S10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N TTL 7411 PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10

    TTL 7410

    Abstract: ua 7411 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 TTL 7411 74LS10 pin configuration 7411 pin configuration 74LS11 function table 74ls 7410 pin configuration
    Text: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products • Triple Three-Input NAND ’10 , AND ('11) Gates Product Specification TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns


    OCR Scan     		PDF 74LS10 74S10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N TTL 7410 ua 7411 PIN CONFIGURATION 7410 PIN CONFIGURATION 7411 TTL 7411 74LS10 pin configuration 7411 pin configuration 74LS11 function table 74ls 7410 pin configuration

    R65F12Q

    Abstract: R6501Q R65F11 rsc-forth pin configuration 74LS00 ROCKWELL R6501Q r6501 74LS04 pin configuration TTL 74ls00 pin configuration logic symbol 74LS00
    Text: R65FRX • R65FKX R65FRX and R65FKx ^ -RSC FORTH Development and Kernel ROMS « Rockwell INTRODUCTION FEATURES The Rockwell Single Chip RSC FORTH System can be con­ figured using the R65F11, R65F12 microcomputers or the R6501Q ROM-less microcomputer. One of these microcom­


    OCR Scan     		PDF R65FRX R65FKX R65FRX R65FKx R65F11, R65F12 R6501Q R65F11 R65FK2 R65F12Q rsc-forth pin configuration 74LS00 ROCKWELL R6501Q r6501 74LS04 pin configuration TTL 74ls00 pin configuration logic symbol 74LS00

    rockwell r65f11ap

    Abstract: 65F12 pin configuration 74LS00 74LS00 pin configuration R65FR1P rockwell eprom R6501Q R65F12Q R65F1 Ram 2k x 32
    Text: R65FRX • R65FKX * R65FRx and R65FKx RSC FORTH Development and Kernel ROMS Rockwell INTRODUCTION FEATURES The Rockwell Single Chip RSC FORTH System can be con­ figured using the R65F11, R65F12 microcomputers or the R6501Q ROM-less microcomputer. One of these microcom­


    OCR Scan     		PDF R65FRX R65FKX R65FRx R65FKx R65FR1 R65F11 R65F12 R65F11/F12 R65FR2 R6501Q rockwell r65f11ap 65F12 pin configuration 74LS00 74LS00 pin configuration R65FR1P rockwell eprom R65F12Q R65F1 Ram 2k x 32

    pin diagram of 74109

    Abstract: 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A
    Text: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74109 33MHz 9mA 74LS109A 33MHz 4mA DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K,


    OCR Scan     		PDF LS109A 1N916, 1N3064, 500ns pin diagram of 74109 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A

    8088 motherboard schematics

    Abstract: Faraday motherboard 8088 PC XT MOTHERBOARD IBM computer schematics 8088 intel 8284 clock generator computer schematics 8088 c8087 ic 8237 dma controler 8088 ram 256K ic dma 8237 8088
    Text: FARADAY 3486347 ELECTRONICS FARADAY INC A4 ELECTRONICS 00D0201 Í>F 34flL,3M7 CORP 84D 00201 h *|~D T- » '33 -03 T -5 2 - 3 3 -1 5 FE2010 PC BUS CPU & PERIPHERAL CONTROLLER IC * 100% Hardware & Software compatible to the IBM-PC * Keyboard Port * 8284 Clock Generator


    OCR Scan     		PDF ij34flL T-52-33-15 FE2010 FE2010) FE20O FE2010 0D00523 8088 motherboard schematics Faraday motherboard 8088 PC XT MOTHERBOARD IBM computer schematics 8088 intel 8284 clock generator computer schematics 8088 c8087 ic 8237 dma controler 8088 ram 256K ic dma 8237 8088