MS-012-AB
Abstract: 14P2P-A SOP14-P-225-1 MS-012AB
Text: 14P2P-A Plastic 14pin 225mil SOP EIAJ Package Code SOP14-P-225-1.27 JEDEC Code MS-012AB Weight g 0.12 Lead Material Cu Alloy e 8 1 7 E Recommended Mount Pad F A Symbol D A2 A1 b y L e L1 HE e1 I2 14 b2 c Detail F A A1 A2 b c D E e HE L L1 y b2 e1 I2 Dimension in Millimeters
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Original
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14P2P-A
14pin
225mil
OP14-P-225-1
MS-012AB
MS-012-AB
14P2P-A
SOP14-P-225-1
MS-012AB
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PDF
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432W6
Abstract: 48P4B hssop 44P3W-R 28P0 5P5T tsop 2-54 42P9R 70P3S-M 479F7G
Text: MITSUBISHI INTEGRATED CIRCUIT PACKAGES LIST OF PACKAGE CODES CLASSIFIED ACCORDING TO PIN NUMBER 1. LIST OF PACKAGE CODES CLASSIFIED ACCORIDING TO PIN NUMBER Pin Count Structure Type Lead Pitch mm 5 P P P P P P C C P P P C P P P P P P P P C P P P P P P P
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Original
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240K6X-A
240P6Y-A
240P6Z-A
255F7F
256F7B
256F7X-A/B
256P6J-E
256P6K-E
272F7X-A/B
281S8-C
432W6
48P4B
hssop
44P3W-R
28P0
5P5T
tsop 2-54
42P9R
70P3S-M
479F7G
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PDF
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IC sj 4558
Abstract: OF 8 pin DIP IC 1251 SJ 1848 SOT-23 HP M5194 sj 4558 HA1631
Text: Product Numbers Product Numbers 1 Product Numbers 2 Renesas New Package Code Destination Standard Logic Part No. Composition P R DP 0008 A F - A HD74HC T 1G 04 CM E • Auxiliary appearance code 1 alphanumeric character; sequential *No general common rules; this code is used to identify lead shape and the like.
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Original
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HD74HC
R18CS0003EJ0200
IC sj 4558
OF 8 pin DIP IC 1251
SJ 1848
SOT-23 HP
M5194
sj 4558
HA1631
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PDF
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74LS11 pin configuration
Abstract: M74HC11P 74LS11 IC pin configuration M74HC11 74LS11 circuit diagram with voltage 4000B 74LS11 M74HC11DP Mitsubishi 74LS11 CMOS 74LS11
Text: M I T S U B I S H I HIGH S P E E D C M O S M 74H C11P M 74H C11D P T R I P L E 3 -IN P U T P O S I T I V E AND G A T E DESCRIPTION PIN T he M74HC11 is a sem iconductor integrated circuit con CONFIGURATION TOP VIEW sisting of th re e 3-in put po sitiv e -lo g ic AND, usable as ne ga
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OCR Scan
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M74HC11P
M74HC11DP
M74HC11
74LS11 pin configuration
74LS11 IC pin configuration
74LS11 circuit diagram with voltage
4000B
74LS11
M74HC11DP
Mitsubishi 74LS11
CMOS 74LS11
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PDF
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74LS04 Hex Inverter Gate function table
Abstract: IC PIN CONFIGURATION OF 74LS04 noise margin ic 74LS04 74LS04 INVERTER CIRCUIT DIAGRAM pin configuration and OF IC 74ls04 CMOS 4000B series device M74HCU04P Mitsubishi 74LS04 pin configuration and description OF IC 74ls04 unbuffered cmos logic application note
Text: M IT S U B IS H I HIGH S P E E D C M O S M 74HCU04P M 74HCU04DP H E X U N B U F F E R E D IN V E R T E R DESCRIPTION PIN CONFIGURATION TOP VIEW T h e M 7 4 H C U 0 4 is a s e m ic o n d u c to r in te g r a te d c irc u it c o n s is tin g of six u n b u ffe r e d in v e rte rs .
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OCR Scan
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M74HCU04P
M74HCU04DP
M74HCU04
4000B
74LS04 Hex Inverter Gate function table
IC PIN CONFIGURATION OF 74LS04
noise margin ic 74LS04
74LS04 INVERTER CIRCUIT DIAGRAM
pin configuration and OF IC 74ls04
CMOS 4000B series device
Mitsubishi 74LS04
pin configuration and description OF IC 74ls04
unbuffered cmos logic application note
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PDF
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI -CDGTL LOGIC} Tl Î>ÊÏ h2M1ÛE7 00l24Tfi □ T MITSUBISHI ALSTTLs M74ALS258P ^ QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER W ITH 3-STATE OUTPUT (INVERTED 6249827 MITSUBISHI 9 1D 12498 CDGTL LOGIC) DESCRIPTION The M 74ALS258P is a sem iconductor integrated cir
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OCR Scan
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00l24Tfi
M74ALS258P
74ALS258P
150mil
16P2P
16-PIN
T-90-20
20P2V
20-PIN
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PDF
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00155L
Abstract: No abstract text available
Text: .^ 0«° M 74 ALS 534 P " 7 ^ ^ -O *7'¿ » S ' MITSUBISHI ALSTTLs OCTAL D-TYPE EDGE-TRIGGERED FLIP FLOP W ITH 3-STATE OUTPUT INVERTED _ 624982 7 MITSUBISHI <DGTL LOGIC) DESCRIPTION 91D 12559 D PIN CONFIGURATION (TOP VIEW) The M74ALS534P is a semiconductor intergrated circuit
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OCR Scan
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M74ALS534P
150mil
16P2P
16-PIN
T-90-20
20P2V
20-PIN
300mil
00155L
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PDF
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI ALSTTLs M 74ALS1035P TËJ MITSUB ISH I {DGTL LOGIC} Q012732 G | HEX NONINVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT / DESCRIPTION PIN CONFIGURATION TOP VIEW ” T h e M 7 4 A L S 1 0 3 5 P is a s e m ic o n d u c to r in te g ra te d c ir c u it c o n s is tin g o f six n o n -inverting b u ffe rs w ith open
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OCR Scan
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74ALS1035P
Q012732
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mll
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PDF
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Untitled
Abstract: No abstract text available
Text: M IT S U B IS H I <DIGITAL ASSP> M 74HC240-1P/FP OCTAL 3-S T A T E IN V E R TIN G B U F F E R /L IN E D R IV E R /L IN E R E C E IV E R DESCRIPTION T h e M 7 4 H C 2 4 0 -1 is a n in te g r a te d c irc u it c h ip c o n s is tin g of PIN CONFIGURATION TOP VIEW
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OCR Scan
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74HC240-1P/FP
T-30-20
14P2P
14-PIN
150mil
16P2P
16-PIN
50mil
20P2V
20-PIN
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PDF
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ci la 7610
Abstract: No abstract text available
Text: c +e MITSUBISHI ALSTTLs . op,00° M 74A L S 620A -1P v ie N v t ^s ^ - 3 _ OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION The M74ALS6Í20A-1P is a semiconductor integrated cir cuit consisting of eight bus transm itter/receiver circuits
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OCR Scan
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M74ALS6
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mil
ci la 7610
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PDF
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M74ALS09
Abstract: M74ALS74 dd127 M74ALS257 M74ALS05 m74als32 m74als561 m74als245 20P2V M74ALS04
Text: MITSUBISHI íDGTL L0GIC3- TI ]>ËÏ bSMTBE? 0 0 i a 4 3 c] 1 T • ■ MITSUBISHI ALSTTLs M74ALS175P ”6 2 4 9 8 2 / MITSUBISHI DGTL LOGIC 91D 1 2 43 9 D QUADRUPLE D-TYPE FLIP FLOP W ITH RESET DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M 74ALS175P is a sem iconductor integrated circuit
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OCR Scan
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M74ALS175P
74ALS175P
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mil
M74ALS09
M74ALS74
dd127
M74ALS257
M74ALS05
m74als32
m74als561
m74als245
M74ALS04
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PDF
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ci la 7610
Abstract: No abstract text available
Text: MITSUBISHI ALSTTLs M 7 4 A LS 6 5 1 P 7 -52-3/ OCTAL BUS TRANSCEIVER/REGISTER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI 91 D 12674 (DGTL LOGIC ) DESCRIPTION The M74ALS651P is a semiconductor integrated circuit consisting of eight bus transceiver/registers with 3-state
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OCR Scan
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M74ALS651P
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mil
ci la 7610
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PDF
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI íDGTL LOGICI TI DEI't.E4*1ñ27 D0ia3flD S MITSUBISHI ALSTTLs M 624 9 82 7 M IT S U B IS H I DG TL L O G IC 7 4 A 91D L S 1 1 3 A P 12380 D DUAL J-K N EG A TIVE EDGE-TRIGGERED FLIP -FLO P W IT H SET T -H (* -o 7 -o y DESCRIPTION PIN CONFIGURATION (TOP VIEW)
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OCR Scan
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74ALS113AP
16P2P
16-PIN
150mil
T-90-20
20P2V
300mil
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PDF
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m74als191p
Abstract: No abstract text available
Text: ÍDGTL LOGIC} 91D TI De | 12446 b241fl27 □ 0 1 2 4 4b ñ r D MITSUBISHI ALSTTLs M 74A LS191P SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER W ITH MODE CONTROL • 7 ^ V ' 5 ' ' ^ >3 DESCRIPTION - o 7 PIN CONFIGURATION TOP VIEW Th e M 7 4 A L S 1 9 1 P is a s e m ic o n d u c to r in te g ra te d c irc u it
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OCR Scan
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b241fl27
LS191P
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mil
m74als191p
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PDF
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI ALSTTLs _ . M MI TSU BISHI -CDGTL LOGIC} 7 4 A L S I Q lit! DEl bdnocc U Duìcvià â P h flT~ HEX INVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT 7 ^ DESCRIPTION / 3 - / ^ PIN CONFIGURATION TOP VIEW Th e M 7 4 A L S 1 0 0 5 P is a s e m ic o n d u c to r in te g ra te d c ir
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OCR Scan
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150mil
16P2P
16-PIN
T-90-20
20P2V
20-PIN
300mll
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PDF
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74ALS640
Abstract: No abstract text available
Text: MITSUBISHI -CDGTL LOGIC} dT | ba^flS? D O i a k b B 4 M ITSUBISHI A L ST T Ls sc* -s s 5 " : . M 7 4 A LS6 4 7 P ,o.9B OCTAL BUS TR A N SC EIV ER /R EG IST ER WITH OPEN COLLECTOR OUTPUT NONINVERTED 6249827 MITSUBISHI CDGTL LOGTC) DESCRIPTION The M74ALS647P is a semiconductor integrated circuit
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OCR Scan
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M74ALS647P
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mil
74ALS640
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PDF
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M74ALS374P
Abstract: dd127 4d40t
Text: MITSUBISHI iDGTL LOGIC} TI 1mF | bSLHÖ27 D0155E5 5 MITSUBISHI ALSTTLs ,oC* M 74A LS374P OCTAL D-TYPE EDGE-TRIGGERED FLIP FLOP W ITH 3-STATE OUTPUT NONINVERTED 6249827 MITSUBISHI 9 1D 12525 (DGTL LOGIC) DESCRIPTION D PIN CONFIGURATION (TOP VIEW) T h e M 7 4 A L S 3 7 4 P is a s e m ic o n d u c to r in te g ra te d c irc u it
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OCR Scan
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D0155E5
LS374P
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mil
M74ALS374P
dd127
4d40t
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PDF
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l54c
Abstract: DT070
Text: MITSUBISHI ÍDGTL LOGIC} "il Ï Ë | ^24^027 0012303 O j ~ MITSUBISHI ALSTTLs M 7 4 A L S 1 1 4 A P T “ 9 6 > ’O t7 ~ O t7 • _ DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP-FLOP W ITH SET. COMMON RESET AND COMMON CLOCK 6249827 MITSUBISHI CDGTL LOGIC DESCRIPTION
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OCR Scan
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M74ALS114AP
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mil
l54c
DT070
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PDF
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI ALSTTLs i # O C * “ M 7 4 A L S 6 Z 3 A - 1 P -7 ^ 5 2 - 3 / OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT NONINVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION The M74ALS623A-1P is a semiconductor integrated circuit c o n s is tin g of eight bus transm itter/receiver
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OCR Scan
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M74ALS623A-1P
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mil
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PDF
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D0-15L
Abstract: LS74AD
Text: 7 z1 % > -'0 '7 -¿ ? S ' M 74ALS873AP ¡C' 3< DUAL 4 -B IT D-TYPE TRANSPARENT LATCH W ITH 3-STATE OUTPUT NONINVERTED 50t° CDGTL LOGIC) DESCRIPTION PIN CONFIGURATION (TOP VIEW) DIR EC T RESET , p " IN P U T I M ° O UTPUT } -q C O N TR O L IN PU T E c
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OCR Scan
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74ALS873AP
M74ALS873AP
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mil
D0-15L
LS74AD
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PDF
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74ALS131
Abstract: 74als245a m74als138p 74als169b 74ALS193D
Text: M IT S U B IS H I -CDGTL L O G I C } TI 0 F | b E 4 ciflE 7 0 D lE 3 flt b |~ _ 6249827 MITSUBISHI I M IT SU B ISH I ALSTTLs M 74ALS131P <DG T L LO GI C 91D 12386 D 3 -L IN E TO 8 -L IN E D E C O D E R /D E M U L T IP L E X E R W IT H A D D R E S S R E G IS T E R
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OCR Scan
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74ALS131P
M74ALS131P
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mll
74ALS131
74als245a
m74als138p
74als169b
74ALS193D
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PDF
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI ALSTTLs M 7 4 A L S 1 0 0 2 À P a D eE| tk24=]aS7 0015712 > | MITSUBISHI IDGTL LOGIC} 11 QUADRUPLE 2-IN P U T PO SITIVE NOR BUFFER 7 ^ V 3 - /S DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M74ALS1002AP is a semiconductor integrated cir cuit consisting of four 2-input positive-logic NOR buffer
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OCR Scan
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M74ALS1002AP
16P2P
16-PIN
150mil
T-90-20
20P2V
20-PIN
300mil
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PDF
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245-1P
Abstract: 74hc245-1
Text: M IT S U B IS H I <DIGITAL ASSP> M 7 4H C 2 4 5 -1P /F P OCTAL 3-S TA T E N O N IN VERTIN G BUS T R A N S C E IV E R DESCRIPTION The M 74HC245-1 is an integrated c irc u it chip consisting of PIN CONFIGURATION TOP VIEW eig h t tra nsceivers w ith no ninverted outputs.
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OCR Scan
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74HC245-1
14P2P
14-PIN
150mil
16P2P
16-PIN
50mil
20P2V
20-PIN
300mll
245-1P
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PDF
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LS1241
Abstract: No abstract text available
Text: MITSUBISHI ALSTTLs l y S2 49 8 2 7 MIT SU BI S HI i T i i • a <DGTL LOGIC « OID ü <i J \ 12737 p D OCTAL B U FFER /LIN E D R IV E R W IT H 3-STATE O UTPUT NONIN V E R TE D ) DESCRIPTION The M74ALS1241AP is a semiconductor integrated circuit consisting of two blocks of buffers with 3-state
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OCR Scan
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M74ALS1241AP
M74ALS241AP
--15mA)
150mil
16P2P
16-PIN
T-90-20
20P2V
20-PIN
LS1241
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PDF
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