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    MILITARY PLASTIC PASIC 3 FAMILY Search Results

    MILITARY PLASTIC PASIC 3 FAMILY Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MR28F010-90 Rochester Electronics LLC 28F010 - 128K X 8 Flash, Mil Temp Visit Rochester Electronics LLC Buy
    MD28F010-90 Rochester Electronics LLC 28F010 - 128K X 8 Flash, Mil Temp Visit Rochester Electronics LLC Buy
    MC80C31BH/B Rochester Electronics LLC 80C31BH - 8-Bit CMOS Microcontroller, Mil Temp Visit Rochester Electronics LLC Buy
    COM1553A/B Rochester Electronics LLC COM1553A/B - Mil-Std-1553B Smart Controller Visit Rochester Electronics LLC Buy
    MC80C31BH Rochester Electronics LLC 80C31BH - 8-Bit CMOS Microcontroller, Mil Temp Visit Rochester Electronics LLC Buy

    MILITARY PLASTIC PASIC 3 FAMILY Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    Military Plastic pASIC 3 Family QuickLogic 60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density Original PDF

    MILITARY PLASTIC PASIC 3 FAMILY Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: QuickSheet#3 Military Plastic Families High Performance Guaranteed Over the Military Temperature Range Military Plastic Highlights • pASIC 1, pASIC 2, pASIC 3, and QuickRAM™ families •200+MHz •Up to 176,000 usable system gates •Up to 25k bits dual-port embedded RAM


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    QL1003-U2 PDF

    CI 3060 elsys

    Abstract: 84-PIN QL3012 QL3025 QL3040 QL3060 QL3060-1PQ208M
    Text: Military Plastic pASIC 3 Family 60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density Military pASIC 3 - 3.3V Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features High Performance and High Density Total of 180 I/O pins •


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    16-bit 456-PBGA PQ208 84-pin PQ208 208-pin CI 3060 elsys QL3012 QL3025 QL3040 QL3060 QL3060-1PQ208M PDF

    PQFP 176

    Abstract: No abstract text available
    Text: Military Plastic pASIC 3 Family 60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density last updated 5/4/2000 Military pASIC 3 - 3.3V Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features High Performance and High Density Total of 180 I/O pins


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    16-bit 456-PBGA PQ208 84-pin PQ208 208-pin PQFP 176 PDF

    Untitled

    Abstract: No abstract text available
    Text: QL8x12 pASIC 1 FAMILY Very-High-Speed IK 3K Gate CMOS FPGA pASIC HIGHLIGHTS Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 100 MHz, and logic cell delays of under 4 ns. High Usable Density - An 8-by-12 array of 96 logic cells provides


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    QL8x12 8-by-12 68-pin 100-pin 16-bit PDF

    CPGA144

    Abstract: No abstract text available
    Text: QL16X24B pASIC 1 FAMILY Very-High-Speed 4K 12K Gate CMOS FPGA PRELIMINARY DATA pASIC HIGHLIGHTS .4000 usable gates, 122 input pins B Very High Speed - ViaLink metal-to-metal programmable-via anti­ fuse technology, allows data path speeds over 150 MHz, and logic cell


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    QL16X24B 16-by-24 QL16x24B QL16x24 CPGA144 PDF

    ACT1020

    Abstract: QL12X16-1PL68C ACT1020 pga pl68c ACT1020 fpga
    Text: bSE D flUICK LOGIC RQD3Q3D 00DQ057 b4T M ü l l I C QL12X16 pASIC 1 FAMILY Very-High-Speed 2K 6K Gate CMOS FPGA pASIC HIGHLIGHTS B Very H igh Speed - ViaLink metal-to-metal progranunable-via anti­ fuse technology, allows counter speeds over 100 MHz, and logic cell


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    00DQ057 QL12X16 12-by-16 68-pin 100-pin 16-bit 12x16 ACT1020 QL12X16-1PL68C ACT1020 pga pl68c ACT1020 fpga PDF

    Untitled

    Abstract: No abstract text available
    Text: 2UICK L O G I C bSE D T D0 3 D3 G DOOODHT 5 7 3 • Û U I C QL8X12 pASIC 1 FAMILY Very-High-Speed 1K (3K Gate CMOS FPGA pASIC HIGHLIGHTS H Very High Speed - ViaLink metal-to-metal programmable-via antifuse technology, allows counter speeds over 100 MHz, and logic


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    QL8X12 8-by-12 68-pin 100-pin 16-bit PDF

    8 bit booth multiplier vhdl code

    Abstract: verilog code for Modified Booth algorithm vhdl code for Booth multiplier Modified Booth Multipliers QL2003 vhdl code for 8bit booth multiplier booth multiplier code in vhdl MTSAM64GZ vhdl code of floating point adder QL16X24BL
    Text: Q U I C K L O G I C ’ S QUICKNEWS CONTENTS VOLUME Tech Talk • pages 2-3 Product Update ■ page 4 Technical Q&A ■ page 5 Software Spotlight ■ page 8 Program Update ■ page 9 New Service ■ page 10 Military Products ■ page 11 Trade Event Schedule


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    QL907-2 8 bit booth multiplier vhdl code verilog code for Modified Booth algorithm vhdl code for Booth multiplier Modified Booth Multipliers QL2003 vhdl code for 8bit booth multiplier booth multiplier code in vhdl MTSAM64GZ vhdl code of floating point adder QL16X24BL PDF

    QL8X12A

    Abstract: pl68c 96
    Text: QL8X12A pASIC 1 FAMILY Very-High-Speed IK 3K Gate CMOS FPGA April 1993 pASIC HIGHLIGHTS RSI Very-High-Speed, Flexible FPGA Architecture - ViaLink metal-tometal, low-resistance antifuse (<50 ohm) interconnect technology allows data path performance over 125 MHz with logic cell delays of under 2.5 ns.


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    QL8X12A 8-by-12 L8X12A QL8x12A QU1KS002 pl68c 96 PDF

    5-input-XOR

    Abstract: 3-input-XOR schematic of TTL XOR Gates TTL XOR Gates cmos XOR Gates verilog code for matrix inversion vhdl code for a up counter in behavioural model 16 bit multiplier VERILOG 3-input-XOR cmos circuit CQFP 208 datasheet
    Text: 10-13 World’s Fastest FPGAs 10-14 X ilin x L a ttic e A lte ra A c te l Q u ic k L o g ic 4.2% 4.3% ing w o y r t G m pa n s e ast y Co ning F 50 Valle Run p o T con ears Sili ree Y Th 8.3% 9.3% 11.7% Quarterly Compounding Revenue Growth, 1995-1997 Highest Industry Growth Rate


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    16-bit 30-day 5-input-XOR 3-input-XOR schematic of TTL XOR Gates TTL XOR Gates cmos XOR Gates verilog code for matrix inversion vhdl code for a up counter in behavioural model 16 bit multiplier VERILOG 3-input-XOR cmos circuit CQFP 208 datasheet PDF

    quicklogic pasic

    Abstract: No abstract text available
    Text: WS * 3 1391 pASIC 1 FAMILY V iaLink™ Technology V ery H igh Speed CMOS FPGAs PRELIMINARY DATA FAMILY HIGHLIGHTS B May 1991 Very High Speed - ViaLink™ Metal-to-metal programmable-via antifuse technology, ensures counter speeds over 100 MHz, and logic


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    16-bit quicklogic pasic PDF

    Untitled

    Abstract: No abstract text available
    Text: bSE » • TOGBDBO DDGDlb? 47T « f l U I C QL8X12A pASIC 1 FAMILY Very-High-Speed IK 3K Gate CMOS FPGA April 1993 pASIC HIGHLIGHTS .3000 total available gates Q Very-High-Speed, Flexible FPGA Arcliitecture - ViaLink metal-tometal, low-resistance antifuse (<50 ohm) interconnect technology allows


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    QL8X12A 8-by-12 8x12A PDF

    dell motherboard schematic

    Abstract: vhdl code for Booth multiplier QL3004 schematic diagram motherboard dell booth multiplier code in vhdl MIPS324Kc intel 4040 HP COMPAQ MOTHERBOARD CIRCUIT diagram 8 bit booth multiplier vhdl code Quickfilter Technologies
    Text: Q U I C K L O G I C ’ S QUICKNEWS CONTENTS VOLUME Tech Talk • page 2 QuickDSP Update ■ page 3 New IP Available ■ page 4 PCI Update ■ page 5 New Eclipse Family ■ page 6 Software Spotlight ■ page 8 New Software Tool ■ page 9 Customer Engineering Q&A


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    QL907-2 dell motherboard schematic vhdl code for Booth multiplier QL3004 schematic diagram motherboard dell booth multiplier code in vhdl MIPS324Kc intel 4040 HP COMPAQ MOTHERBOARD CIRCUIT diagram 8 bit booth multiplier vhdl code Quickfilter Technologies PDF

    pasic 3

    Abstract: QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060
    Text: pASIC 3 FPGA Family Data Sheet •••••• Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • Up to 60,000 usable PLD gates with up to 316 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths


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    16-bit pasic 3 QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060 PDF

    vhdl code for a grey-code counter

    Abstract: RAM256X4 electronic stethoscope project QL4090 QL5064 vhdl code of 4 bit comparator
    Text: Q U I C K L O G I C ’ S QUICKNEWS CONTENTS VOLUME Tech Talk with John Birkner • pages 2-3 QL4090-M New Military Product ■ page 4 QL2003 at Elevated Temperatures ■ page 5 Marketing Update ■ page 6 Technical Notes ■ page 7 Technical Q&A ■ pages 8-9


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    QL4090-M QL2003 QL907-2 vhdl code for a grey-code counter RAM256X4 electronic stethoscope project QL4090 QL5064 vhdl code of 4 bit comparator PDF

    intel 4040

    Abstract: TQFP 144 PACKAGE 100-PIN 84-PIN PF100 PF144 PL84 QL2003 QL2003-1PF100C QL2003-1PF144C
    Text: QL2003 3,000 Gate pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility PRELIMINARY DATA pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance


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    QL2003 intel 4040 TQFP 144 PACKAGE 100-PIN 84-PIN PF100 PF144 PL84 QL2003 QL2003-1PF100C QL2003-1PF144C PDF

    QL24X32B-1PQ208C

    Abstract: PF144 PQ208
    Text: QL24x32B Wild Cat 8000 Very-High-Speed 8K 24K Gate CMOS FPGA 2 .8000 usable gates, 180 I/O pins Very High Speed – ViaLinkTM metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


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    QL24x32B 24-by-32 144pin 208-pin Viewlog-55, 24x32B PQ208 M/883C MIL-STD-883D PF144 QL24X32B-1PQ208C PF144 PDF

    QuickLogic ql16x24b-1pl84c

    Abstract: No abstract text available
    Text: QL16X24B WildCat 4000 Very-High-Speed 4K 12K Gate CMOS FPGA pASIC HIGHLIGHTS B Very High Speed - ViaLink metal-to-metal programmable-via anti­ fuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. H High Usable Density - A 16-by-24 array of 384 logic cells provides


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    QL16X24B 16-by-24 84-pin 144-pin 169-pin 16-bit QL16x24B 16x24B QuickLogic ql16x24b-1pl84c PDF

    Untitled

    Abstract: No abstract text available
    Text: QL16X24B W ild ca t 4000 Very-High-Speed 4K 12K Gate CMOS FPGA pASIC HIGHLIGHTS .4000 usable gates, 122 input pins Q Very High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


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    QL16X24B 16-by-24 84-pin 144-pin 169-pin 16-bit 16x24B TGD3030 00G025S PDF

    ACT1020

    Abstract: CY7C383A CY7C384A Military Plastic pASIC 3 Family
    Text: CY7C383A CY7C384A CYPRESS Very High Speed 2K 6K Gate CMOS FPGA — Fast, fully automatic place and route — Waveform simulation with back annotated net delays — PC and workstation platforms Robust routing resources — Fully automatic place and route of


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    CY7C383A CY7C384A 84-pin 100-pin 16-bit CY7C384Aâ ACT1020 CY7C384A Military Plastic pASIC 3 Family PDF

    QP-PL84G

    Abstract: QL8X12B-2pl68c TQFP 100 pin Socket CQFJ 84 socket 68 pin plcc socket view bottom PL84 QL12X16B QL8X12B pASIC 1 Family QL12x16B "pin compatible"
    Text: pASIC Designer Programmer User's Guide May 1997 Copyright Information Copyright 1991-1997 QuickLogic Corporation. All rights reserved. The information contained in this manual and the accompanying software program are protected by copyright; all rights are reserved by QuickLogic Corporation.


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    Win32s, QP-PL84G QL8X12B-2pl68c TQFP 100 pin Socket CQFJ 84 socket 68 pin plcc socket view bottom PL84 QL12X16B QL8X12B pASIC 1 Family QL12x16B "pin compatible" PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C383A CY7C384A *= CYPRESS Very High Speed 2K 6K Gate CMOS FPGA — Fast, fully autom atic place and route — Waveform simulation with back annotated net delays — PC and workstation platforms Robust routing resources — Fully automatic place and route of


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    CY7C383A CY7C384A CY7C383A) CY7C384A) CY7C384A-0G 84-Pin CY7C384A-0JC 84-Lead CY7C384Aâ 100-Pin PDF

    Untitled

    Abstract: No abstract text available
    Text: QL2007 7,000 Gate pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C PRELIMINARY DATA pASIC 2 HIGHLIGHTS -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis


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    QL2007 PQ208C 84-pin PI-144 144-pin PQ208 208-pin PB256 256-pin PDF

    Untitled

    Abstract: No abstract text available
    Text: m u iit im ü . iv iu M U c iy , n u y u ö i i u , Revision: Monday, May 23,1994 CY7C383A CY7C384A W CYPRESS Very High Speed 2K 6K Gate CMOS FPGA — Fast, fully automatic place and route — Waveform simulation with back annotated net delays — PC and workstation platforms


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    CY7C383A CY7C384A CY7C383A) CY7C384A) 0D14575 PDF