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    QLogic Corporation QL3060-3PQ208C

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    Bristol Electronics QL3060-3PQ208C 191
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    Quest Components QL3060-3PQ208C 152
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    QLogic Corporation QL3060-3PB456I-4270

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    QuickLogic Corporation QL3060-3PB456I

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    QLOG QL3060-3PQ208C

    FIELD PROGRAMMABLE GATE ARRAY, 1584 CLBS, 60000 GATES, 225MHZ, 1584-CELL, CMOS, PQFP208
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    Quest Components QL3060-3PQ208C 47
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    QuickLogic Corporation QL3060-3PB456I-4749

    QLGQL3060-3PB456I-4749 PASIC 3 (Alt: QL3060-3PB456I-4749)
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    Avnet Asia QL3060-3PB456I-4749 22 Weeks 24
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    QL3060 Datasheets (59)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    QL3060 Unknown 60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density Original PDF
    QL3060 QuickLogic High Performance and High Density with Low Cost and Complete Flexibility Original PDF
    QL3060 QuickLogic High-Speed, Low Power, Instant-On, High Security FPGA Original PDF
    QL3060-0PB456C QuickLogic 60,000 usable PLD gate pASIC 3 FPGA combining high performance and high density. Original PDF
    QL3060-0PB456C QuickLogic 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Original PDF
    QL3060-0PB456I QuickLogic 60,000 usable PLD gate pASIC 3 FPGA combining high performance and high density. Original PDF
    QL3060-0PB456I QuickLogic 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Original PDF
    QL3060-0PB456M QuickLogic 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Original PDF
    QL3060-0PB456M QuickLogic 60,000 usable PLD gate pASIC 3 FPGA combining high performance and high density. Original PDF
    QL3060-0PQ208C QuickLogic 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Original PDF
    QL3060-0PQ208C QuickLogic 60,000 usable PLD gate pASIC 3 FPGA combining high performance and high density. Original PDF
    QL3060-0PQ208I QuickLogic 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Original PDF
    QL3060-0PQ208I QuickLogic 60,000 usable PLD gate pASIC 3 FPGA combining high performance and high density. Original PDF
    QL3060-0PQ208M QuickLogic 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Original PDF
    QL3060-0PQ208M QuickLogic 60,000 usable PLD gate pASIC3 FPGA combining high performance and high density. Original PDF
    QL3060-1PB456C QuickLogic 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Original PDF
    QL3060-1PB456C QuickLogic 60,000 usable PLD gate pASIC 3 FPGA combining high performance and high density. Original PDF
    QL3060-1PB456I QuickLogic 60,000 usable PLD gate pASIC 3 FPGA combining high performance and high density. Original PDF
    QL3060-1PB456I QuickLogic 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Original PDF
    QL3060-1PB456M QuickLogic 60,000 usable PLD gate pASIC 3 FPGA combining high performance and high density. Original PDF

    QL3060 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    208-PIN

    Abstract: 456-PIN
    Text: QL3060 - pASIC 3 FPGATM 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density QL3060 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os ■ 16-bit counter speeds over 300 MHz, data path speeds over


    Original     		PDF QL3060 16-bit 208-PIN 456-PIN

    AE21 ARRAY DIODE

    Abstract: QL3060 AD 149 AE9 AA23 PQ208 QL3060-1PB456C QL3060-1PQ208C B14 ON
    Text: QL3060 pASIC 3 FPGA Data Sheet •••••• 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths


    Original     		PDF QL3060 16-bit AE21 ARRAY DIODE AD 149 AE9 AA23 PQ208 QL3060-1PB456C QL3060-1PQ208C B14 ON

    Untitled

    Abstract: No abstract text available
    Text: QL3060 / QL3060R 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA March, 1998 2 … 60,000 usable PLD gates, 316 I/O pins High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os -16-bit counter speeds over 250 MHz, data path speeds over 275 MHz


    Original     		PDF QL3060 QL3060R -16-bit

    CI 3060 elsys

    Abstract: QL3060 PB256 PQ208 QL3040 QL3040-1PQ208C 344RAM
    Text: QL3060 / QL3060R 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA February, 1998 2 … 60,000 usable PLD gates, 316 I/O pins 25,344 bit RAM Option High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os


    Original     		PDF QL3060 QL3060R -16-bit CI 3060 elsys PB256 PQ208 QL3040 QL3040-1PQ208C 344RAM

    CI 3060 elsys

    Abstract: AA23 QL3060 QL3060-1PB456C QL3060-1PQ208C
    Text: QL3060 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 4 pASIC 3 HIGHLIGHTS … 60,000 usable PLD gates, 316 I/O pins High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz


    Original     		PDF QL3060 -16-bit QL3060-rev. CI 3060 elsys AA23 QL3060 QL3060-1PB456C QL3060-1PQ208C

    A23 862-1

    Abstract: AD 149 AE9 CI 3060 elsys AA23 PQ208 QL3060 QL3060-1PB456C QL3060-1PQ208C
    Text: QL3060 pASIC 3 FPGA Data Sheet •••••• 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths


    Original     		PDF QL3060 16-bit A23 862-1 AD 149 AE9 CI 3060 elsys AA23 PQ208 QL3060-1PB456C QL3060-1PQ208C

    Untitled

    Abstract: No abstract text available
    Text: QL3060 - pASIC 3 FPGATM 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density last updated 5/15/2000 QL3060 - pASIC 3 FPGA DEVICE HIGHLIGHTS Device Highlights Device Highlights High Performance & High Density • 60,000 Usable PLD Gates with 316 I/Os


    Original     		PDF QL3060 16-bit

    QL3004

    Abstract: PLCC-84 QL3060 QL2003 QL2005 QL2007 QL2009 QL3012 QL3025 QL3040
    Text: QuickSheet#4 pASIC FPGA Families High-Speed, Low Power, Instant-On, High Security FPGAs pASIC Family Highlights • High performance over 400 MHz • 100% routability and pin stability • Instant-On capability • High security and reliability • Low power


    Original     		PDF 400MHz QL1004-U1 1210JHGDA QL3004 PLCC-84 QL3060 QL2003 QL2005 QL2007 QL2009 QL3012 QL3025 QL3040

    QL4090

    Abstract: pASIC 1 Family 160CQFP 208-CQFP
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit V144-TQFP QL24x32B QL4090 pASIC 1 Family 160CQFP 208-CQFP

    208CQFP

    Abstract: No abstract text available
    Text: QL2007  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance


    Original     		PDF QL2007 -16-bit l144-TQFP QL24x32B 208-PQFP 208-CQFP 125oC MIL-STD-883 208CQFP

    asynchronous fifo vhdl

    Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024
    Text: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com


    Original     		PDF

    pasic 3

    Abstract: QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060
    Text: pASIC 3 FPGA Family Data Sheet •••••• Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • Up to 60,000 usable PLD gates with up to 316 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths


    Original     		PDF 16-bit pasic 3 QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060

    240-PIN

    Abstract: AA23 QL3060-1PQ240C QL4090 QL4090-1PB456C QL4090-1PQ208C AB24-AB25
    Text: QL4090 90,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM Last Updated: April 15, 1999 QuickRAM HIGHLIGHTS … 90,000 usable PLD gates, 316 I/O pins High Performance and High Density - 90,000 Usable PLD Gates with 316 I/Os


    Original     		PDF QL4090 16-bit 152-bit QL4090 240-PIN AA23 QL3060-1PQ240C QL4090-1PB456C QL4090-1PQ208C AB24-AB25

    FPGA 144 CPGA ASIC

    Abstract: QL5032 144TQFP PACKAGE 160-CQFP PLCC 144
    Text: p ASIC QUICKLOGIC DEVELOPMENT TOOLS Part Number Product Name QS-QWK-PC QuickWorks QS-QTL-WS QuickTools for Workstations N/A QuickWorks - Lite N/A QuickMap QT-DFP-PC-A 1 DeskFab Programmer Kit N/A Synosys Interface Kit N/A Viewlogic Interface Kit N/A Mentor Interface Kit


    Original     		PDF 44-PLCC 68-PLCC 68-CPGA 100-TQFP 84-PLCC 84-CPGA FPGA 144 CPGA ASIC QL5032 144TQFP PACKAGE 160-CQFP PLCC 144

    100TQFP

    Abstract: 344RAM QL3040
    Text: QL2003  3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance


    Original     		PDF QL2003 -16-bit l144-TQFP QL24x32B 208-PQFP 208-CQFP 125oC MIL-STD-883 100TQFP 344RAM QL3040

    QL4090

    Abstract: No abstract text available
    Text: QL12X16B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …2,000 usable ASIC gates, 88 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL12X16B 12-by-16 68-pin 84-pin 100-pin 16-bit Synops144-TQFP QL24x32B 208-PQFP QL4090

    Untitled

    Abstract: No abstract text available
    Text: QuickSheet#3 Military Plastic Families High Performance Guaranteed Over the Military Temperature Range Military Plastic Highlights • pASIC 1, pASIC 2, pASIC 3, and QuickRAM™ families •200+MHz •Up to 176,000 usable system gates •Up to 25k bits dual-port embedded RAM


    Original     		PDF QL1003-U2

    QL3012

    Abstract: QL3025 QL3040 QL3060 QL4016 QL4090 footprint pqfp 208 QuickLogic Military FPGA Introduction
    Text: QuickLogic Military FPGA Introduction Military FPGA Combining High Performance and High Density Military FPGA Introduction DEVICE HIGHLIGHTS Device Highlights Military FPGA • Mil Std 883 and Mil Temp Ceramic ■ Mil Temp Plastic Guaranteed -55 to +125oC


    Original     		PDF 125oC 152-bit 16-bit -55oC, QL3012 QL3025 QL3040 QL3060 QL4016 QL4090 footprint pqfp 208 QuickLogic Military FPGA Introduction

    144-TQFP

    Abstract: 256PBGA CPGA QL3012 QL3025 QL3040 QL3060 144TQFP 100-TQFP
    Text: pASIC pASIC DEVELOPMENT TOOLS Part Number Product Name QS-QWK-PC QuickWorks QS-QTL-PC QuickTools-PC Plus QS-QTL-WS QuickTools for Workstations N/A QuickChip N/A QuickMap QT-DFP-PC-A 1 DeskFab Programmer Kit N/A Synosys Interface Kit N/A Viewlogic Interface Kit


    Original     		PDF 44-PLCC 68-PLCC 100-TQFP 84-PLCC 84-CPGA3 144-TQFP 144-TQFP 256PBGA CPGA QL3012 QL3025 QL3040 QL3060 144TQFP 100-TQFP

    ulc xc3030

    Abstract: PQFP 176 Xilinx XC3090 altera EP300 EPM7128 Temic ulc xc3030 EPM7128 PLCC PLSI2032 Actel A1020 PLUS405
    Text: ULC Reference Guide This reference guide lists most devices available for conversion. This list is not exhaustive, as new devices are added regularly. Additional devices not shown in this list may also be supported. Updated versions are available on the TEMIC web site. Check with factory if


    Original     		PDF ULC/A1010 ULC/A1020 ulc xc3030 PQFP 176 Xilinx XC3090 altera EP300 EPM7128 Temic ulc xc3030 EPM7128 PLCC PLSI2032 Actel A1020 PLUS405

    intel 4040

    Abstract: QL3004 transistor equivalent table 557 cmos 4040 datasheet general cross references QL5064 QL4009 QL4016 QL4058 QL5030
    Text: EMBEDDED STANDARD PRODUCT A GENERATION AHEAD ! The Vialink Antifuse in 0.35µ µm CMOS QuickLogic Corporation 1277 Orleans Dr. Sunnyvale, CA 94089-1138 General Information: Applications Hotline FAX: EMAIL: WEB SITE: 408 990-4000 (408) 990-4100 (408) 990-4040


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: QL3060 / QL3060R 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA . 60,000 usable PLD gates, 316 I/O pins S High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os -16-bit counter speeds over 250 MHz, data path speeds over 275 MHz


    OCR Scan     		PDF QL3060 QL3060R -16-bit

    Untitled

    Abstract: No abstract text available
    Text: QL3060 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 pASIC 3 HIGHLIGHTS . 60,000 usable PLD gates, 316 I/O pins S High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz


    OCR Scan     		PDF QL3060 -16-bit

    Untitled

    Abstract: No abstract text available
    Text: QL3040 40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 pASIC 3 HIGHLIGHTS . 40,000 usable PLD gates, 252 I/O pins S High Performance and High Density -40,000 Usable PLD Gates with 252 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz


    OCR Scan     		PDF QL3040 -16-bit