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    74LVC3G Search Results

    74LVC3G Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LVC3G06DCUT Texas Instruments Triple Inverter Buffer/Driver with Open-Drain Output 8-VSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LVC3G07DCUTG4 Texas Instruments Triple Buffer/Driver With Open-Drain Output 8-VSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LVC3G14DCUTG4 Texas Instruments Triple Schmitt-Trigger Inverter 8-VSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LVC3G34DCUR Texas Instruments Triple Buffer Gate 8-VSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LVC3GU04DCTR Texas Instruments Triple Inverter Gate 8-SM8 -40 to 125 Visit Texas Instruments Buy
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    74LVC3G Price and Stock

    Texas Instruments SN74LVC3G14DCUR

    IC INVERT SCHMITT 3CH 3IN 8VSSOP
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    DigiKey SN74LVC3G14DCUR Cut Tape 74,970 1
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    Texas Instruments SN74LVC3G07DCT3

    IC BUFFER NON-INVERT 5.5V SM8
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    DigiKey SN74LVC3G07DCT3 Digi-Reel 4,330 1
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    Nexperia 74LVC3G14GT,115

    IC INVERT SCHMITT 3CH 3INP 8XSON
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    Diodes Incorporated 74LVC3G34V8-7

    IC BUF NON-INVERT 3CH 3INP 8SSOP
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    Diodes Incorporated 74LVC3G14V8-7

    IC INVERT SCHMITT 3CH 3IN 8VSSOP
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    74LVC3G Datasheets (253)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LVC3G04 Philips Semiconductors Triple inverter Original PDF
    74LVC3G04DC Philips Semiconductors Triple inverter Original PDF
    74LVC3G04DC,125 NXP Semiconductors 74LVC3G04 - IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 2.30 MM, PLASTIC, MO-187, SOT765-1, VSSOP-8, Gate Original PDF
    74LVC3G04DC,125 NXP Semiconductors Triple inverter - Description: 3.3V Triple PicoGate Inverter ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.7@3.3V ns; Voltage: 1.65-5.5; Package: SOT765-1 (VSSOP8); Container: Reel Pack, Reverse, Reverse Original PDF
    74LVC3G04DC-G NXP Semiconductors 74LVC3G04DC - Triple inverter - Description: 3.3V Triple PicoGate Inverter ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.7@3.3V ns; Voltage: 1.65-5.5 Original PDF
    74LVC3G04DC-G NXP Semiconductors Triple inverter - Description: 3.3V Triple PicoGate Inverter ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.7@3.3V ns; Voltage: 1.65-5.5 Original PDF
    74LVC3G04DC-Q100H NXP Semiconductors 74LVC3G04DC-Q100 - 74LVC3G04DC-Q100 - Triple inverter Original PDF
    74LVC3G04DP Philips Semiconductors Triple inverter Original PDF
    74LVC3G04DP,125 NXP Semiconductors 74LVC3G04 - IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 3 MM, PLASTIC, SOT505-2, TSSOP-8, Gate Original PDF
    74LVC3G04DP,125 NXP Semiconductors Triple inverter - Description: 3.3V Triple PicoGate Inverter ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.7@3.3V ns; Voltage: 1.65-5.5; Package: SOT505-2 (TSSOP8); Container: Reel Pack, Reverse, Reverse Original PDF
    74LVC3G04DP-G NXP Semiconductors 74LVC3G04DP - Triple inverter - Description: 3.3V Triple PicoGate Inverter ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.7@3.3V ns; Voltage: 1.65-5.5 Original PDF
    74LVC3G04DP-G NXP Semiconductors Triple inverter - Description: 3.3V Triple PicoGate Inverter ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.7@3.3V ns; Voltage: 1.65-5.5 Original PDF
    74LVC3G04DP-Q100125 NXP Semiconductors INVERTER, LVC/LCX/Z SERIES Original PDF
    74LVC3G04DP-Q100H NXP Semiconductors 74LVC3G04DP-Q100 - 74LVC3G04DP-Q100 - Triple inverter Original PDF
    74LVC3G04GD,125 NXP Semiconductors 74LVC3G04 - IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PDSO8, 3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT996-2, XSON-8, Gate Original PDF
    74LVC3G04GF,115 NXP Semiconductors IC INVERTER TRPL BUFFER XSON8 Original PDF
    74LVC3G04GM NXP Semiconductors 74LVC3G04 - IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PQCC8, 1.60 X 1.60 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-255, SOT902-1, QFN-8, Gate Original PDF
    74LVC3G04GM NXP Semiconductors Triple inverter Original PDF
    74LVC3G04GM,115 NXP Semiconductors 74LVC3G04GM - Triple inverter, SOT902-1 Package, Standard Marking, Reel Pack, SMD, 7" Original PDF
    74LVC3G04GM,125 NXP Semiconductors 74LVC3G04 - IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PBCC8, 1.60 X 1.60 MM, 0.50 MM HEIGHT, PLASTIC, MO-255, SOT902-1, XQFN-8, Gate Original PDF
    ...

    74LVC3G Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    MARKING V7 6-PIN

    Abstract: No abstract text available
    Text: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 11 — 6 July 2012 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.


    Original     		74LVC3G14 74LVC3G14 MARKING V7 6-PIN PDF

    74LVC3G14

    Abstract: 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187
    Text: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 07 — 12 June 2008 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of


    Original     		74LVC3G14 74LVC3G14 74LVC3G14DC 74LVC3G14DP 74LVC3G14GM 74LVC3G14GT JESD22-A114E MO-187 PDF

    74LVC3G07

    Abstract: 74LVC3G07DC 74LVC3G07DP 74LVC3G07GM 74LVC3G07GT
    Text: 74LVC3G07 Triple buffer with open-drain output Rev. 7 — 9 August 2010 Product data sheet 1. General description The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.


    Original     		74LVC3G07 74LVC3G07 74LVC3G07DC 74LVC3G07DP 74LVC3G07GM 74LVC3G07GT PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 10 — 14 June 2012 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		74LVC3G04 74LVC3G04 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple inverter Rev. 10 — 6 July 2012 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		74LVC3GU04 74LVC3GU04 JESD22-A114F JESD22-A115-A PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G14 Triple inverting Schmitt trigger with 5 V tolerant input Rev. 12 — 9 April 2013 Product data sheet 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.


    Original     		74LVC3G14 74LVC3G14 PDF

    MO-187

    Abstract: 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E
    Text: 74LVC3G04 Triple inverter Rev. 05 — 5 October 2007 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		74LVC3G04 74LVC3G04 MO-187 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E PDF

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC3G04 Triple inverter Preliminary specification File under Integrated Circuits, IC24 2003 Aug 19 Philips Semiconductors Preliminary specification Triple inverter 74LVC3G04 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 5.5 V


    Original     		74LVC3G04 JESD8B/JESD36 EIA/JESD22-A114-A EIA/JESD22-A115-A OT505-2 OT765-1 PDF

    mnb120

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple inverter Rev. 01 — 12 May 2004 Product data sheet 1. General description The 74LVC3GU04 is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these


    Original     		74LVC3GU04 74LVC3GU04 EIA/JESD22-A114-B EIA/JESD22-A115-A mnb120 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G34 Triple buffer gate Rev. 01 — 29 April 2004 Product data sheet 1. General description The 74LVC3G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of


    Original     		74LVC3G34 74LVC3G34 PDF

    74LVC3G17

    Abstract: 74LVC3G17DC 74LVC3G17DP 74LVC3G17GM 74LVC3G17GT JESD22-A114E MO-187
    Text: 74LVC3G17 Triple non-inverting Schmitt trigger with 5 V tolerant input Rev. 05 — 13 March 2008 Product data sheet 1. General description The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free


    Original     		74LVC3G17 74LVC3G17 74LVC3G17DC 74LVC3G17DP 74LVC3G17GM 74LVC3G17GT JESD22-A114E MO-187 PDF

    74LVC3GU04

    Abstract: 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT JESD22-A114E MO-187 VU04
    Text: 74LVC3GU04 Triple inverter Rev. 06 — 4 March 2008 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		74LVC3GU04 74LVC3GU04 JESD8B/JESD36 JESD22-A114E JESD22-A115-A 74LVC3GU04DC 74LVC3GU04DP 74LVC3GU04GM 74LVC3GU04GT MO-187 VU04 PDF

    74LVC3G06

    Abstract: 74LVC3G06DC 74LVC3G06DP 74LVC3G06GM 74LVC3G06GT JESD22-A114E MO-187
    Text: 74LVC3G06 Triple inverter with open-drain output Rev. 07 — 12 March 2009 Product data sheet 1. General description The 74LVC3G06 provides three inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.


    Original     		74LVC3G06 74LVC3G06 74LVC3G06DC 74LVC3G06DP 74LVC3G06GM 74LVC3G06GT JESD22-A114E MO-187 PDF

    74LVC3G04

    Abstract: 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E MO-187
    Text: 74LVC3G04 Triple inverter Rev. 07 — 16 June 2008 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		74LVC3G04 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E MO-187 PDF

    74LVC3G34

    Abstract: 74LVC3G34DC 74LVC3G34DP 74LVC3G34GD 74LVC3G34GM 74LVC3G34GT
    Text: 74LVC3G34 Triple buffer Rev. 8 — 2 September 2010 Product data sheet 1. General description The 74LVC3G34 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G34 as a translator in a mixed 3.3 V and 5 V environment.


    Original     		74LVC3G34 74LVC3G34 74LVC3G34DC 74LVC3G34DP 74LVC3G34GD 74LVC3G34GM 74LVC3G34GT PDF

    74LVC3G06

    Abstract: 74LVC3G06DC 74LVC3G06DP 74LVC3G06GT MO-187 1.4541
    Text: 74LVC3G06 Triple inverter with open-drain output Rev. 03 — 01 February 2005 Product data sheet 1. General description The 74LVC3G06 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.


    Original     		74LVC3G06 74LVC3G06 74LVC3G06DC 74LVC3G06DP 74LVC3G06GT MO-187 1.4541 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G06 Triple inverter with open-drain output Rev. 10 — 27 June 2012 Product data sheet 1. General description The 74LVC3G06 provides three inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.


    Original     		74LVC3G06 74LVC3G06 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple inverter Rev. 9 — 23 November 2011 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of


    Original     		74LVC3GU04 74LVC3GU04 JESD22-A114F JESD22-A115-A PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 10 — 14 June 2012 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		74LVC3G04 74LVC3G04 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G17 Triple non-inverting Schmitt trigger with 5 V tolerant input Rev. 8 — 21 September 2011 Product data sheet 1. General description The 74LVC3G17 provides three non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free


    Original     		74LVC3G17 74LVC3G17 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G07 Triple buffer with open-drain output Rev. 11 — 9 April 2013 Product data sheet 1. General description The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.


    Original     		74LVC3G07 74LVC3G07 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3GU04 Triple unbuffered inverter Rev. 11 — 9 April 2013 Product data sheet 1. General description The 74LVC3GU04 is a triple unbuffered inverter. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.


    Original     		74LVC3GU04 74LVC3GU04 JESD22-A114F JESD22-A115-A PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 11 — 2 April 2013 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		74LVC3G04 74LVC3G04 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G07 Triple buffer with open-drain output Rev. 8 — 19 October 2011 Product data sheet 1. General description The 74LVC3G07 provides three non-inverting buffers. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.


    Original     		74LVC3G07 74LVC3G07 PDF