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    74LVC3G04GM Search Results

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    74LVC3G04GM Price and Stock

    Rochester Electronics LLC 74LVC3G04GM,125

    IC INVERTER 3CH 3-INP 8XQFN
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    DigiKey 74LVC3G04GM,125 Bulk 4,274
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    Nexperia 74LVC3G04GM,125

    IC INVERTER 3CH 3-INP 8XQFN
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    DigiKey 74LVC3G04GM,125 Reel
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    74LVC3G04GM,125 Digi-Reel 1
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    74LVC3G04GM,125 Cut Tape
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    Rochester Electronics 74LVC3G04GM,125 3,660 1
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    Chip One Stop 74LVC3G04GM,125 Cut Tape 68
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    NXP Semiconductors 74LVC3G04GM,125

    74LVC3G04GM - Inverter, LVC/LCX/Z Series, 3-Func, 1-Input, CMOS, PQCC8 '
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    Rochester Electronics 74LVC3G04GM,125 55,096 1
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    NXP Semiconductors 74LVC3G04GM-G

    INVERTER; Temperature Grade: AUTOMOTIVE; Terminal Form: NO LEAD; No. of Terminals: 8; Package Code: QCCN; Package Shape: SQUARE;
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    Vyrian 74LVC3G04GM-G 364
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    NXP Semiconductors 74LVC3G04GM,115

    INVERTER; Temperature Grade: AUTOMOTIVE; Terminal Form: NO LEAD; No. of Terminals: 8; Package Code: VQCCN; Package Shape: SQUARE;
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    Vyrian 74LVC3G04GM,115 287
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    74LVC3G04GM Datasheets (5)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LVC3G04GM NXP Semiconductors 74LVC3G04 - IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PQCC8, 1.60 X 1.60 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-255, SOT902-1, QFN-8, Gate Original PDF
    74LVC3G04GM NXP Semiconductors Triple inverter Original PDF
    74LVC3G04GM,115 NXP Semiconductors 74LVC3G04GM - Triple inverter, SOT902-1 Package, Standard Marking, Reel Pack, SMD, 7" Original PDF
    74LVC3G04GM,125 NXP Semiconductors 74LVC3G04 - IC LVC/LCX/Z SERIES, TRIPLE 1-INPUT INVERT GATE, PBCC8, 1.60 X 1.60 MM, 0.50 MM HEIGHT, PLASTIC, MO-255, SOT902-1, XQFN-8, Gate Original PDF
    74LVC3G04GM,125 NXP Semiconductors Triple inverter; Package: SOT902-1 (XQFN8U); Container: Reel Pack, Reverse, Reverse Original PDF

    74LVC3G04GM Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 10 — 14 June 2012 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original
    74LVC3G04 74LVC3G04 PDF

    MO-187

    Abstract: 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E
    Text: 74LVC3G04 Triple inverter Rev. 05 — 5 October 2007 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


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    74LVC3G04 74LVC3G04 MO-187 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E PDF

    74LVC3G04

    Abstract: 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E MO-187
    Text: 74LVC3G04 Triple inverter Rev. 07 — 16 June 2008 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original
    74LVC3G04 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT JESD22-A114E MO-187 PDF

    marking code E2 logic gate

    Abstract: SN74LVC3G04DCUR 74AUP3G04 74LVC3G04 NC7NP04 NC7NZ04 NL37WZ04 SN74LVC3G04 "MARKING CODE" 3Y
    Text: SLG74LB3G04 GreenLIBTM TRIPLE INVERTER GATE General Description Features The GreenLIB provides the triple inverter gate. This device is • Pb-Free / RoHS Compliant fully specified for partial-power-down applications using Ioff. • Halogen-Free The Ioff circuitry disables the outputs, preventing damaging


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    SLG74LB3G04 000-0074LB3G04-10 marking code E2 logic gate SN74LVC3G04DCUR 74AUP3G04 74LVC3G04 NC7NP04 NC7NZ04 NL37WZ04 SN74LVC3G04 "MARKING CODE" 3Y PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 10 — 14 June 2012 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original
    74LVC3G04 74LVC3G04 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 11 — 2 April 2013 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original
    74LVC3G04 74LVC3G04 PDF

    SOT-833

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 04 — 20 March 2007 Product data sheet 1. General description The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


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    74LVC3G04 74LVC3G04 SOT-833 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 9 — 23 November 2011 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


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    74LVC3G04 74LVC3G04 PDF

    74LVC3G04

    Abstract: 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT
    Text: 74LVC3G04 Triple inverter Rev. 8 — 10 November 2010 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original
    74LVC3G04 74LVC3G04 74LVC3G04DC 74LVC3G04DP 74LVC3G04GM 74LVC3G04GT PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 02 — 18 October 2004 Product data sheet 1. General description The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original
    74LVC3G04 74LVC3G04 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74LVC3G04 Triple inverter Rev. 06 — 3 March 2008 Product data sheet 1. General description The 74LVC3G04 provides three inverting buffers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original
    74LVC3G04 74LVC3G04 JESD8B/JESD36 PDF