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    AMD XC5VFX130T-1FF1738I

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    XC5VFX130T Datasheets (15)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    XC5VFX130T-1FF1738C Xilinx Virtex-5 Multi-Platform FPGAs, Package: 1FF1738C Original PDF
    XC5VFX130T-1FF1738CES Xilinx Virtex-5 Multi-Platform FPGAs, Package: 1FF11738CES Original PDF
    XC5VFX130T-1FF1738I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 840 I/O 1738FCBGA Original PDF
    XC5VFX130T-1FFG1738C Xilinx Virtex-5 Multi-Platform FPGAs, Package: 1FFG1738C Original PDF
    XC5VFX130T-1FFG1738CES Xilinx Virtex-5 Multi-Platform FPGAs, Package: 1FFG11738CES Original PDF
    XC5VFX130T-1FFG1738I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 840 I/O 1738FCBGA Original PDF
    XC5VFX130T-2FF1738C Xilinx Virtex-5 Multi-Platform FPGAs, Package: 2FF1738C Original PDF
    XC5VFX130T-2FF1738C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 840 I/O 1738FCBGA Original PDF
    XC5VFX130T-2FF1738CES Xilinx Virtex-5 Multi-Platform FPGAs, Package: 2FF11738CES Original PDF
    XC5VFX130T-2FF1738I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 840 I/O 1738FCBGA Original PDF
    XC5VFX130T-2FFG1738C Xilinx Virtex-5 Multi-Platform FPGAs, Package: 2FFG1738C Original PDF
    XC5VFX130T-2FFG1738CES Xilinx Virtex-5 Multi-Platform FPGAs, Package: 2FFG1738CES Original PDF
    XC5VFX130T-2FFG1738I Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 840 I/O 1738FCBGA Original PDF
    XC5VFX130T-3FF1738C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 840 I/O 1738FCBGA Original PDF
    XC5VFX130T-3FFG1738C Xilinx Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 840 I/O 1738FCBGA Original PDF

    XC5VFX130T Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    XC5VLX50T-1FFG665C

    Abstract: ff1156 VIRTEX-5 DDR2 controller FFG1156 VIRTEX-5 DDR PHY Virtex-5 Ethernet development Virtex-5 LXT Ethernet DSP48E SRL16 XC5VLX220
    Text: R DS100 v5.0 February 6, 2009 Virtex-5 Family Overview Product Specification General Description The Virtex -5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice


    Original     		DS100 36-Kbit UG197) UG200) UG194) XC5VLX50T-1FFG665C ff1156 VIRTEX-5 DDR2 controller FFG1156 VIRTEX-5 DDR PHY Virtex-5 Ethernet development Virtex-5 LXT Ethernet DSP48E SRL16 XC5VLX220 PDF

    Numonyx StrataFlash JS28F256P30

    Abstract: JS28F256P30 28f256p30 Numonyx 28f256p30 JS28F256P30T NUMONYX xilinx bpi 28F256P Numonyx P30 XAPP973 Numonyx
    Text: Application Note: Virtex-5 FPGAs R XAPP973 v1.4 March 8, 2010 Summary Indirect Programming of BPI PROMs with Virtex-5 FPGAs Author: Stephanie Tapp Virtex -5 FPGAs and ISE® software support configuration from and programming of industrystandard, parallel NOR flash memory (BPI PROMs). Industry standard BPI PROMs are an


    Original     		XAPP973 Numonyx StrataFlash JS28F256P30 JS28F256P30 28f256p30 Numonyx 28f256p30 JS28F256P30T NUMONYX xilinx bpi 28F256P Numonyx P30 XAPP973 Numonyx PDF

    Virtex-5 LX50T

    Abstract: SVF pcf VIRTEX-5 FX70T VIRTEX-5 LX110 FPGA Virtex 6 pin configuration Virtex 5 CF Virtex-5 LX50 DSP48E UG191 XC5VLX220
    Text: Virtex-5 FPGA Configuration User Guide User Guide [optional] UG191 v3.7 June 24, 2009 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG191 Virtex-5 LX50T SVF pcf VIRTEX-5 FX70T VIRTEX-5 LX110 FPGA Virtex 6 pin configuration Virtex 5 CF Virtex-5 LX50 DSP48E UG191 XC5VLX220 PDF

    ff1136

    Abstract: FF665 UG203 ff676 xc5vlx20t-ff323 capacitor package DSP48E FF1153 FF1156 FF1759
    Text: Virtex-5 FPGA PCB Designer’s Guide UG203 v1.4 April 20, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG203 ff1136 FF665 UG203 ff676 xc5vlx20t-ff323 capacitor package DSP48E FF1153 FF1156 FF1759 PDF

    MP21608S221A

    Abstract: UG198 FERRITE-220 GTX tile oversampling recovered clock ROSENBERGER verilog code for linear interpolation filter aurora GTX BLM15HB221SN1 gearbox rev maxim DVB
    Text: Virtex-5 FPGA RocketIO GTX Transceiver User Guide UG198 v2.1 November 17, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG198 MP21608S221A UG198 FERRITE-220 GTX tile oversampling recovered clock ROSENBERGER verilog code for linear interpolation filter aurora GTX BLM15HB221SN1 gearbox rev maxim DVB PDF

    RTL 8188

    Abstract: RAMB18SDP RAMB36 UG190 XC5VLX XC5VLX220T XC5VLX85T RAM32X1D SRLC32E xilinx jtag cable spartan 3
    Text: Virtex-5 FPGA User Guide UG190 v5.2 November 5, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG190 SSTL18 RTL 8188 RAMB18SDP RAMB36 UG190 XC5VLX XC5VLX220T XC5VLX85T RAM32X1D SRLC32E xilinx jtag cable spartan 3 PDF

    XC6VLX130T

    Abstract: XC6VLX195T XC5VL110T XC5VL155T PCI33 XC6VLX240T XC5vfx70t XC5VL330T XC4VSX35 ff1156
    Text: XI LI NX VI RTEX -6 FAM I LY FPGAS Virtex-6 LXT FPGAs Virtex-6 SXT FPGAs Optimized for High-Performance Logic and DSP with Low-Power Serial Connectivity 1.0 Volt, 0.9 Volt Part Number EasyPath FPGA Cost Reduction Solutions(1) Logic Resources XC6VLX760T


    Original     		XC6VLX75T XC6VLX130T XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760T XC6VSX315T XC6VSX475T XC6VHX250T XC6VLX130T XC6VLX195T XC5VL110T XC5VL155T PCI33 XC6VLX240T XC5vfx70t XC5VL330T XC4VSX35 ff1156 PDF

    VIRTEX-5 DDR2 pcb design

    Abstract: 16 channel synchronous lvds ADC interface xilinx virtex5 XC5VLX50 FFG676 VIRTEX-5 DDR2 controller GTP ethernet XC5VFX70 ug195 XC5VFX130T
    Text: R DS100 v4.2 May 7, 2008 Virtex-5 Family Overview Advance Product Specification General Description The Virtex -5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains four distinct platforms (sub-families), the most choice


    Original     		DS100 36-Kbit UG193) DSP48E UG191) UG195) VIRTEX-5 DDR2 pcb design 16 channel synchronous lvds ADC interface xilinx virtex5 XC5VLX50 FFG676 VIRTEX-5 DDR2 controller GTP ethernet XC5VFX70 ug195 XC5VFX130T PDF

    Xilinx spartan xc3s400_ft256

    Abstract: XC3S400_FT256 XC3S400PQ208 XC3S250EPQ208 xc3s400TQ144 XC3S400FT256 xc3s1400afg676 XC3S700AFG484 XC3S500EPQ208 XC3S200FT256
    Text: Memory Interface Solutions User Guide UG086 v3.3 December 2, 2009 R R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,


    Original     		UG086 DQS10 DQS11 DQS12 DQS13 DQS14 DQS15 DQS16 DQS17 Xilinx spartan xc3s400_ft256 XC3S400_FT256 XC3S400PQ208 XC3S250EPQ208 xc3s400TQ144 XC3S400FT256 xc3s1400afg676 XC3S700AFG484 XC3S500EPQ208 XC3S200FT256 PDF

    XCF04S

    Abstract: xcf16pfs XCF32P-VOG48 XCF02S RELIABILITY REPORT 48-pin TSOP Package VO48 Xilinx Spartan-II 2.5V FPGA Family FSG48 XCF02S pcb
    Text: 47 Platform Flash In-System Programmable Configuration PROMs R DS123 v2.13.1 April 3, 2008 Product Specification Features • In-System Programmable PROMs for Configuration of Xilinx FPGAs • ♦ 3.3V Supply Voltage Low-Power Advanced CMOS NOR Flash Process


    Original     		DS123 XCF04S xcf16pfs XCF32P-VOG48 XCF02S RELIABILITY REPORT 48-pin TSOP Package VO48 Xilinx Spartan-II 2.5V FPGA Family FSG48 XCF02S pcb PDF

    R 804

    Abstract: XC5VFX70
    Text: Virtex-5 FPGA Data Sheet: DC and Switching Characteristics R DS202 v4.9 December 19, 2008 Advance Product Specification Virtex-5 FPGA Electrical Characteristics Virtex -5 FPGAs are available in -3, -2, -1 speed grades, with -3 having the highest performance. Virtex-5 FPGA DC


    Original     		DS202 R 804 XC5VFX70 PDF

    XC5VLX50T-1FFG665C

    Abstract: virtex 5 fpga ethernet to pc DSP48E VIRTEX-5 VIRTEX-5 DDR2 controller SRL16 XC5VLX220 XC5VLX330 Virtex Analog to Digital Converter UG195
    Text: R DS100 v4.4 September 23, 2008 Virtex-5 Family Overview Advance Product Specification General Description The Virtex -5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice


    Original     		DS100 36-Kbit UG194) UG197) UG200) XC5VLX50T-1FFG665C virtex 5 fpga ethernet to pc DSP48E VIRTEX-5 VIRTEX-5 DDR2 controller SRL16 XC5VLX220 XC5VLX330 Virtex Analog to Digital Converter UG195 PDF

    Virtex-6 reflow

    Abstract: WS609 xc3s3400a xcv400e-b UG116 XCS20XL pqg208 UG-116 XC1702L XCE4VSX25 xc3s500e fg320
    Text: Device Reliability Report First Quarter 2010 UG116 v5.9 May 4, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, p∅ost, or transmit the


    Original     		UG116 611GU FGG676 FFG1152 Virtex-6 reflow WS609 xc3s3400a xcv400e-b UG116 XCS20XL pqg208 UG-116 XC1702L XCE4VSX25 xc3s500e fg320 PDF

    XQR5VFX130

    Abstract: CF1752 XQR5V DIODE BA40 BA5 marking AJ-42 diode Aa42 FF1738 AJ3125 FP1760
    Text: Virtex-5QV FPGA Packaging and Pinout Advance Specification Second Quarter 2009 [optional] UG520 v1.1 September 22, 2010 UG520 (v1.1) September 22, 2010 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development


    Original     		UG520 XQR5VFX130 CF1752 XQR5V DIODE BA40 BA5 marking AJ-42 diode Aa42 FF1738 AJ3125 FP1760 PDF

    XAPP951

    Abstract: M25PXX NUMONYX xilinx spi virtex 5 x95108 virtex 4 vs spartan 3e spi flash SPARTAN 6 spi numonyx spi In Circuit Serial Programming X9510 UG332
    Text: Application Note: Spartan-3E and Virtex-5 FPGAs Configuring Xilinx FPGAs with SPI Serial Flash XAPP951 v1.3 September 23, 2010 Summary Author: Stephanie Tapp This application note discusses the Serial Peripheral Interface (SPI) configuration mode introduced in the Virtex -5 and Spartan®-3E FPGA families. The required connections to


    Original     		XAPP951 XAPP951 M25PXX NUMONYX xilinx spi virtex 5 x95108 virtex 4 vs spartan 3e spi flash SPARTAN 6 spi numonyx spi In Circuit Serial Programming X9510 UG332 PDF

    Numonyx StrataFlash JS28F256P30

    Abstract: JS28F256P30 28f256p30 intel 28f256p30 JS28F256P30T NUMONYX xilinx bpi 28F256P XAPP973 Numonyx 28f256p30 JS28F256P
    Text: Application Note: Virtex-5 FPGAs R XAPP973 v1.3 March 4, 2009 Summary Indirect Programming of BPI PROMs with Virtex-5 FPGAs Author: Stephanie Tapp Virtex -5 FPGAs and ISE® software support configuration from and programming of industrystandard, parallel NOR flash memory (BPI PROMs). Industry standard BPI PROMs are an


    Original     		XAPP973 Numonyx StrataFlash JS28F256P30 JS28F256P30 28f256p30 intel 28f256p30 JS28F256P30T NUMONYX xilinx bpi 28F256P XAPP973 Numonyx 28f256p30 JS28F256P PDF

    csb 485 E2

    Abstract: Xilinx XCF08P XCF01SVO20 XCF32P XCF128X fs48 xc3s400 pinout XCF32PVO48 DS123 VO48
    Text: 48 Platform Flash In-System Programmable Configuration PROMs R DS123 v2.16 November 14, 2008 Product Specification Features • In-System Programmable PROMs for Configuration of Xilinx FPGAs • ♦ 3.3V Supply Voltage Low-Power Advanced CMOS NOR Flash Process


    Original     		DS123 VOG20 csb 485 E2 Xilinx XCF08P XCF01SVO20 XCF32P XCF128X fs48 xc3s400 pinout XCF32PVO48 DS123 VO48 PDF

    RTL 8188

    Abstract: RAMB18SDP differential amplifier cascade output UG190 vhdl code hamming ecc t3 bel 187 TRANSISTOR REPLACEMENT GUIDE 20303 RAMB36 FPGA Virtex 6
    Text: Virtex-5 FPGA User Guide UG190 v5.0 June 19, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG190 SSTL18 RTL 8188 RAMB18SDP differential amplifier cascade output UG190 vhdl code hamming ecc t3 bel 187 TRANSISTOR REPLACEMENT GUIDE 20303 RAMB36 FPGA Virtex 6 PDF

    XCV100 TQ144

    Abstract: XCS20XL pqg208 XC3S700AN FGG484 WS609 x2 type ac capacitor UG-116 xc3s200an pqg208 SPARTAN-3 XC3S400 PQ208 XC3S200 RELIABILITY REPORT UG116
    Text: Device Reliability Report First Quarter 2009 [optional] UG116 v5.5 June 15, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG116 611GU FGG676 FFG1152 XCV100 TQ144 XCS20XL pqg208 XC3S700AN FGG484 WS609 x2 type ac capacitor UG-116 xc3s200an pqg208 SPARTAN-3 XC3S400 PQ208 XC3S200 RELIABILITY REPORT UG116 PDF

    XCF128XFTG64C

    Abstract: XCF128XFT64C xcf128x FX200T LX330 xc5vlx85t XCF128XFTG64CES VIRTEX-5 xc5vlx50t XC5VSX95T XCF32P
    Text: PLATFORM FLASH XL Xilinx XCF128X FAQ 1. What is Platform Flash XL? Platform Flash XL is the newest configuration storage device for Xilinx and has been optimized for use with Xilinx Virtex-5 FPGAs. The Platform Flash XL has the industry’s highest performance,


    Original     		XCF128X 128Mb. XCF128XFT64C) XCF128XFTG64C) XCF128XFT64CES XCF128XFTG64CES XCF128XFT64C XCF128XFTG64C FX200T LX330 xc5vlx85t VIRTEX-5 xc5vlx50t XC5VSX95T XCF32P PDF

    camera-link to hd-SDI converter

    Abstract: Virtex-4QV DS-KIT-FX12MM1-G AES-S6DEV-LX150T-G VHDL code for ADC and DAC SPI with FPGA spartan 3 ADQ0007 XC6SL AES-XLX-V4FX-PCIE100-G SPARTAN-3 XC3S400 based MXS3FK ADS-XLX-SP3-EVL400
    Text: Product Selection Guides Table of Contents February 2010 Virtex Series . 2 Spartan Series . 6


    Original     		PDF

    XAPP864

    Abstract: verilog hdl code for triple modular redundancy ML507 xilinx uart verilog code for spartan 3a frame_ecc ML505 RAM SEU Xilinx VIRTEX-5 xc5vlx50 ug191 uart verilog testbench
    Text: Application Note: Virtex-5 Family SEU Strategies for Virtex-5 Devices Author: Ken Chapman XAPP864 v2.0 April 1, 2010 Summary Xilinx devices are designed to have an inherently low susceptibility to single event upsets (SEUs). This application note provides a substantial discussion of strategies and


    Original     		XAPP864 XAPP864 verilog hdl code for triple modular redundancy ML507 xilinx uart verilog code for spartan 3a frame_ecc ML505 RAM SEU Xilinx VIRTEX-5 xc5vlx50 ug191 uart verilog testbench PDF

    UG161

    Abstract: XCF128X COOLRUNNER-II example led xc6slx75t XC3SD3400A xc5vlx220t XCF02S RELIABILITY REPORT virtex 6 XC6VSX475T xc6slx75 XC6VLX365T
    Text: Platform Flash PROM User Guide UG161 v1.5 October 26, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the


    Original     		UG161 XAPP694, XAPP544, XCF02S/XCF04S XAPP389, UG002, UG071, UG191, UG332, UG360, UG161 XCF128X COOLRUNNER-II example led xc6slx75t XC3SD3400A xc5vlx220t XCF02S RELIABILITY REPORT virtex 6 XC6VSX475T xc6slx75 XC6VLX365T PDF

    RAMB36SDP

    Abstract: frame_ecc FIFO36 BA284 XAPP1073 A330 RAMB36E1 read back JESD89A WP332 adiru
    Text: Application Note: Virtex-5 and Virtex-6 FPGA Families NSEU Mitigation in Avionics Applications Authors: Ching Hu and Suhail Zain XAPP1073 v1.0 May 17, 2010 Summary Neutron-induced single event upset (NSEU) is a known phenomenon in the memory structures of modern ICs used in terrestrial applications. With current and next-generation aircraft


    Original     		XAPP1073 RAMB36SDP frame_ecc FIFO36 BA284 XAPP1073 A330 RAMB36E1 read back JESD89A WP332 adiru PDF