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    VIRTEX - II FAMILY FPGA Search Results

    VIRTEX - II FAMILY FPGA Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MC68020CEH25E-G Rochester Electronics LLC Microprocessor, 32-Bit, MC68000 Family Visit Rochester Electronics LLC Buy
    MC68020ERC25/B Rochester Electronics LLC Microprocessor, 32-Bit, MC68000 Family Visit Rochester Electronics LLC Buy
    EP1800GM-75/B Rochester Electronics LLC EP1800 - Classic Family EPLD Visit Rochester Electronics LLC Buy
    TE512S32-25LC Rochester Electronics LLC TE512S32 - Field Programmable Gate Array, CMOS, PQFP128 Visit Rochester Electronics LLC Buy
    TE505S16-40QC-G Rochester Electronics LLC TE505S16 - Field Programmable Gate Array, CMOS, PQFP208 Visit Rochester Electronics LLC Buy

    VIRTEX - II FAMILY FPGA Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    fast sram 100mhz

    Abstract: CLK180 SRAM timing CY7C1302V25 XAPP262 XC2V250 qdr sram di35 vhdl code for DCM
    Text: Application Note: Virtex-II Family R Quad DataRate QDR SRAM Interface for Virtex-II Devices XAPP262 (v1.0) January 15, 2001 Summary The Virtex -II family of FPGAs provides access to a variety of on-chip and off-chip RAM resources. In addition to the on-chip distributed RAM and block RAM features, Virtex-II FPGAs


    Original     		PDF XAPP262 CY17C1302V25 fast sram 100mhz CLK180 SRAM timing CY7C1302V25 XAPP262 XC2V250 qdr sram di35 vhdl code for DCM

    Sibercore

    Abstract: CLK180 XAPP254 Sibercore Technologies longest prefix match CAM
    Text: Application Note: Virtex-II Family R Virtex-II SiberBridge Author: Ratima Kataria & the SiberCore Applications Engineering Group XAPP254 v1.1 February 25, 2005 Summary Designed to be implemented in a Virtex -II FPGA, the Virtex-II SiberBridge is a register


    Original     		PDF XAPP254 32-bit Sibercore CLK180 XAPP254 Sibercore Technologies longest prefix match CAM

    Sibercore

    Abstract: XAPP254 Sibercore Technologies ternary content addressable memory CLK180 SiberCAM longest prefix match CAM
    Text: Application Note: Virtex-II Family R The Virtex-II SiberBridge Author: Ratima Kataria & the SiberCore Applications Engineering Group XAPP254 v1.0 January 12, 2001 Summary Designed to be implemented in a Virtex -II FPGA, the Virtex-II SiberBridge is a register


    Original     		PDF XAPP254 32-bit Sibercore XAPP254 Sibercore Technologies ternary content addressable memory CLK180 SiberCAM longest prefix match CAM

    cordic design for fixed angle rotation

    Abstract: CORDIC in xilinx CORDIC system generator xilinx CORDIC MAGNITUDE code for scale free cordic cordic design for fixed angle of rotation code for cordic cordic algorithm CORDIC tanh fpga polar architecture
    Text: CORDIC v2.0 DS249 v1.5 March 28, 2003 Product Specification Features • Word Serial architectural configuration for small area • Available for all Virtex , Virtex-E, Virtex-II, Virtex-II Pro™, Spartan™-II, Spartan-IIE and Spartan-3 FPGA family members


    Original     		PDF DS249 cordic design for fixed angle rotation CORDIC in xilinx CORDIC system generator xilinx CORDIC MAGNITUDE code for scale free cordic cordic design for fixed angle of rotation code for cordic cordic algorithm CORDIC tanh fpga polar architecture

    K103-K

    Abstract: 684 k 100 XC2V80 XC2V8000 XC2V40 XC2V1500 XC2V2000 XC2V4000 XC2V10000
    Text: Xilinx FPGAs Virtexª, Virtex-II, Virtex-E and Virtex-EM FPGAs Continued Virtex-II Family (Continued) FPGA Package Options and User I/O FG IOBs XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 XC2V10000 896 Ñ


    Original     		PDF XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 K103-K 684 k 100 XC2V8000 XC2V10000

    XAPP623

    Abstract: LVCMOS25 PCI33 UG112 XAPP646 XAPP653 XAPP659
    Text: Application Note: Virtex-II Pro / Virtex-II Pro X Family R Virtex-II Pro / Virtex-II Pro X 3.3V I/O Design Guidelines XAPP659 v1.7 April 24, 2007 Summary This application note describes guidelines on interfacing 3.3V I/O standards (PCI, LVTTL, and LVCMOS) in a Virtex -II Pro / Virtex-II Pro X system design. Topics include


    Original     		PDF XAPP659 XAPP653 XAPP646, XAPP623 LVCMOS25 PCI33 UG112 XAPP646 XAPP659

    x9214

    Abstract: DS252
    Text: Reed-Solomon Decoder v4.0 DS252 v1.0 March 28, 2003 Product Specification Features • High-speed, compact Reed-Solomon Decoder • Available for all Virtex , Virtex-E, Virtex-II, Virtex-II Pro™, Spartan™-II, Spartan-IIE and Spartan-III FPGA family members


    Original     		PDF DS252 x9214 DS252

    X9205

    Abstract: XC2VP
    Text: Reed-Solomon Encoder v4.0 DS251 v1.0 March 28, 2003 Product Specification Features Pinout • Available for all Virtex , Virtex-E, Virtex-II, Virtex-II Pro™, Spartan™-II, Spartan-IIE and Spartan-III FPGA family members Port names for the core module are shown in Figure 1 and


    Original     		PDF DS251 X9205 XC2VP

    Applications of "XOR Gate"

    Abstract: mixed signal fpga datasheet XAPP776 Pulse generator circuit
    Text: Application Note: Virtex-II Pro X Family R XAPP776 v1.0 April 4, 2005 AC Coupling Bypass for High-Speed Digitizing on Virtex-II Pro X FPGAs Author: Tim Hagen Summary This application note describes a method for bypassing the AC coupling in Virtex -II Pro X


    Original     		PDF XAPP776 Applications of "XOR Gate" mixed signal fpga datasheet XAPP776 Pulse generator circuit

    XAPP649

    Abstract: Champion Technologies vhdl code direct digital synthesizer vhdl code for All Digital PLL verilog code of 8 bit comparator
    Text: Application Note: Virtex-II Pro Family R XAPP649 v1.2 May 14, 2007 SONET Rate Conversion in Virtex-II Pro Devices Author: Nick Sawyer and Francesco Contu Summary This application note targets Virtex-II Pro designs where there is a requirement to directly


    Original     		PDF XAPP649 16-bit 8b/10b 20-bit XAPP649 Champion Technologies vhdl code direct digital synthesizer vhdl code for All Digital PLL verilog code of 8 bit comparator

    DES Encryption

    Abstract: XC2V1000 XC2V3000 XC2V40 XC2V6000 wp1550 configuration bits
    Text: White Paper: Virtex-II Family R WP155 v1.1 April 22, 2002 Triple DES Encryption in Selected Virtex-II Devices This white paper describes Triple DES Encryption for the Virtex -II devices listed in the following table: Device Engineering Sample (ES) (JTAG IDCODE Version


    Original     		PDF WP155 XC2V40 XC2V1000 XC2V3000 XC2V6000 DES Encryption XC2V1000 XC2V3000 XC2V40 XC2V6000 wp1550 configuration bits

    XAPP136

    Abstract: virtex ucf file 6 No Turnaround RAM 1k SRAM Static SRAM XILINX/UCF example for FTP BG432 virtex 5 ddr data path DRAM controller memory FPGA "network interface cards"
    Text: Application Note: Virtex Series and Spartan-II Family Synthesizable 200 MHz ZBT SRAM Interface R XAPP136 v2.0 January 10, 2000 Author: Shekhar Bapat Summary The Virtex series and the Spartan™-II family of FPGAs provide access to a variety of on-chip


    Original     		PDF XAPP136 XAPP136 virtex ucf file 6 No Turnaround RAM 1k SRAM Static SRAM XILINX/UCF example for FTP BG432 virtex 5 ddr data path DRAM controller memory FPGA "network interface cards"

    vhdl code for 8 bit barrel shifter

    Abstract: vhdl code for 4 bit barrel shifter verilog code for 16 bit barrel shifter verilog code for barrel shifter 32 bit barrel shifter vhdl 8 bit barrel shifter vhdl code vhdl code for barrel shifter verilog code for 64 bit barrel shifter barrel shifter using verilog 8 bit barrel shifter
    Text: Application Note: Virtex-II Family R XAPP195 v1.1 August 17, 2004 Implementing Barrel Shifters Using Multipliers Author: Paul Gigliotti Summary The Virtex -II family of platform FPGAs is the first FPGA family to have multipliers embedded into the FPGA fabric. These multipliers, besides offering very fast and flexible multipliers,


    Original     		PDF XAPP195 vhdl code for 8 bit barrel shifter vhdl code for 4 bit barrel shifter verilog code for 16 bit barrel shifter verilog code for barrel shifter 32 bit barrel shifter vhdl 8 bit barrel shifter vhdl code vhdl code for barrel shifter verilog code for 64 bit barrel shifter barrel shifter using verilog 8 bit barrel shifter

    xilinx MTBF

    Abstract: X094 XAPP094 XC4005E XC2VP4
    Text: Application Note: Virtex-II Pro Family R Metastable Recovery in Virtex-II Pro FPGAs Author: Peter Alfke XAPP094 v3.0 February 10, 2005 Summary This application note describes the probability of a metastable event occuring in a Xilinx Virtex -II Pro FPGA. The test circuit measures the Mean Time Between Failure (MTBF) of


    Original     		PDF XAPP094 XC4005E, xilinx MTBF X094 XAPP094 XC4005E XC2VP4

    verilog prbs generator

    Abstract: mixed signal fpga datasheet XAPP776 DESIGN AND IMPLEMENTATION OF PRBS GENERATOR
    Text: Product Obsolete or Under Obsolescence Application Note: Virtex-II Pro X Family R XAPP776 v1.0 April 4, 2005 AC Coupling Bypass for High-Speed Digitizing on Virtex-II Pro X FPGAs Author: Tim Hagen Summary This application note describes a method for bypassing the AC coupling in Virtex -II Pro X


    Original     		PDF XAPP776 verilog prbs generator mixed signal fpga datasheet XAPP776 DESIGN AND IMPLEMENTATION OF PRBS GENERATOR

    vhdl sdram

    Abstract: CLK180 FD64 PC-100 SRL16 XAPP200 virtex 5 ddr data path V300BG432 signal path designer
    Text: Application Note: Virtex Series and Spartan-II Family R XAPP200 v2.2 February 18, 2000 Synthesizable 1.6 GBytes/s DDR SDRAM Controller Author: Jennifer Tran Summary The DLLs and the SelectI/O features in the Virtex™ architecture and Spartan™-II family


    Original     		PDF XAPP200 64-bit XAPP179, vhdl sdram CLK180 FD64 PC-100 SRL16 XAPP200 virtex 5 ddr data path V300BG432 signal path designer

    XAPP200

    Abstract: vhdl sdram CLK180 FD64 PC-100 SRL16 Xilinx Spartan-II 2.5V FPGA Family signal path designer
    Text: Application Note: Virtex Series and Spartan-II Family R XAPP200 v2.3 March 21, 2000 Synthesizable 1.6 GBytes/s DDR SDRAM Controller Author: Jennifer Tran Summary The DLLs and the SelectI/O features in the Virtex™ architecture and Spartan™-II family


    Original     		PDF XAPP200 64-bit XAPP200 vhdl sdram CLK180 FD64 PC-100 SRL16 Xilinx Spartan-II 2.5V FPGA Family signal path designer

    MT47H16M16FG

    Abstract: XAPP678 MT47H16M16FG-37E MT47H16M16FG-37E IT XAPP678C DDR2 SDRAM component data sheet DDR2 SDRAM sstl_18 DDR2 sstl_18 class XAPP688 XAPP549
    Text: Application Note: Virtex-II Pro Family R XAPP549 v1.2 April 30, 2007 DDR2 SDRAM Memory Interface for Virtex-II Pro FPGAs Author: Maria George Summary This application note describes a DDR2 SDRAM memory interface for Virtex -II Pro FPGAs. Architecture This DDR2 SDRAM memory interface has a 72-bit data width. The data bus must be placed on


    Original     		PDF XAPP549 72-bit MT47H16M16FG-37E, com/pdf/datasheets/dram/ddr2/256MbDDR2 mig007 MT47H16M16FG XAPP678 MT47H16M16FG-37E MT47H16M16FG-37E IT XAPP678C DDR2 SDRAM component data sheet DDR2 SDRAM sstl_18 DDR2 sstl_18 class XAPP688 XAPP549

    PPC405

    Abstract: 4926N XAPP640 4021N EICC405CRITINPUTIRQ 4021-N 9022N
    Text: Application Note: Virtex-II Pro Family R Timing Constraints for Virtex-II Pro Designs XAPP640 v1.1 January 16, 2003 Summary This application note discusses the usage of timing constraints in a Virtex-II Pro design with the PowerPC™ 405 (PPC405) processor. The interaction of the timing constraints with the


    Original     		PDF XAPP640 PPC405) PPC405, PPC405 4926N XAPP640 4021N EICC405CRITINPUTIRQ 4021-N 9022N

    16 bit multiplier VERILOG

    Abstract: multiplier accumulator MAC code VHDL multiplier accumulator MAC code verilog vhdl code for accumulator addition accumulator MAC code verilog 16 bit multiplier VERILOG circuit multiplier accumulator unit with VHDL verilog code for 16 bit multiplier MULT18X18S XAPP636
    Text: Application Note: Virtex-II Family R XAPP636 v1.4 June 24, 2004 Summary Optimal Pipelining of I/O Ports of the Virtex-II Multiplier Author: Markus Adhiwiyogo This application note and reference design describes a high-speed, optimized implementation of a Virtex -II pipelined multiplier primitive (MULT18X18 and MULT18X18S) implemented in


    Original     		PDF XAPP636 MULT18X18 MULT18X18S) xapp636 16 bit multiplier VERILOG multiplier accumulator MAC code VHDL multiplier accumulator MAC code verilog vhdl code for accumulator addition accumulator MAC code verilog 16 bit multiplier VERILOG circuit multiplier accumulator unit with VHDL verilog code for 16 bit multiplier MULT18X18S

    vhdl code gold sequence code

    Abstract: vhdl code for gold code vhdl code for pn sequence generator pn sequence generator verilog code 16 bit LFSR lfsr galois gold sequence generator gold code generator GOLD CODE XAPP217
    Text: Application Note: Virtex Series, Virtex-II Series, and Spartan-II family R Gold Code Generators in Virtex Devices Author: Maria George, Mujtaba Hamid, and Andy Miller XAPP217 v1.1 January 10, 2001 Summary Gold code generators are used extensively in Code Division Multiple Access (CDMA) systems


    Original     		PDF XAPP217 SRL16 SRL16 41-stage 41-stage, SRL16Es. vhdl code gold sequence code vhdl code for gold code vhdl code for pn sequence generator pn sequence generator verilog code 16 bit LFSR lfsr galois gold sequence generator gold code generator GOLD CODE XAPP217

    XAPP653

    Abstract: LVDCI33 1N4004 LT1763 LT1763CS8 LVCMOS25 PCI33 QS3861 TPS7301 XAPP646
    Text: Application Note: Virtex-II Pro Family R Using 3.3V I/O Guidelines in a Virtex-II Pro Design XAPP659 v1.3 May 6, 2003 Summary This application note describes guidelines on interfacing a 3.3V I/O standard (PCI, LVTTL, and LVCMOS) in a Virtex-II Pro system design. Topics include overshoot/undershoot design


    Original     		PDF XAPP659 XAPP653 LVDCI33 1N4004 LT1763 LT1763CS8 LVCMOS25 PCI33 QS3861 TPS7301 XAPP646

    verilog code for serial multiplier

    Abstract: XAPP656 sequential multiplier Vhdl 8 bit sequential multiplier VERILOG RocketIO
    Text: Application Note: Virtex-II Pro Family Using the Virtex-II Pro RocketIO MGT for Frequency Multiplication R XAPP656 v1.0 November 5, 2004 Summary The Virtex-II Pro RocketIO™ multi-gigabit transceiver (MGT) is extremely useful to the system designer in its usual role as a high-speed serial communications device. Many designs,


    Original     		PDF XAPP656 20-bit Non-50/50 com/bvdocs/appnotes/xapp656 verilog code for serial multiplier XAPP656 sequential multiplier Vhdl 8 bit sequential multiplier VERILOG RocketIO

    active noise cancellation for FPGA

    Abstract: quad video processor
    Text: R Introduction to the Virtex-II Pro FPGA Family The Next Logical Revolution The Virtex-II Pro Platform FPGA solution is the most technically sophisticated silicon and software product development in the history of the programmable logic industry. The goal


    Original     		PDF UG012 active noise cancellation for FPGA quad video processor