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    MBT- 100K

    Abstract: No abstract text available
    Text: SYNERGY SEMI CON D U CT OR *SYNERGY S7E ]> • T0013A1 0000033 SE2 I SY10484-3.5/4/5/6 4K x 4 ECL RAM SY100484-3.5/4/5/6 SY101484-3.5/4/5/6 SEMICONDUCTOR -T -H é -Z 3 '0 8 ■ FEATURES Address access tim e, tAA: 3.5/4/5/6ns max. Chip select access tim e, tAc: 3ns max.


    OCR Scan     		PDF T0013A1 500ps SY10484-3 SY100484-3 SY101484-3 SY10/100/101484 16384-bit 4096-words-by-4-bits 10K/100K SY100age MBT- 100K

    Untitled

    Abstract: No abstract text available
    Text: LOW-POWER HEX TTL-TO-PECL TRANSLATOR SYNERGY SY100S391 SEMICONDUCTOR FEATURES DESCRIPTION • Operates from a single +5V supply The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this


    OCR Scan     		PDF SY100S391 SY100S391 T0013A1 00022b0 D24-1 391FC F24-1

    850C

    Abstract: F100K SY100S364
    Text: <& SY100S364 16-INPUT MULTIPLEXER SYNERGY S EM IC O N D U C TO R FEATURES • ■ Max. propagation delay of 1300ps min. of -63mA ■ ESD protection of 2000V ■ Ie e ■ Industry standard 100K ECL levels ■ Extended supply voltage option: V ee = -4.2V to -5.5V


    OCR Scan     		PDF 16-INPUT SY100S364 1300ps -63mA F100K SY100S364 SY100S364DC D24-1 SY100S364FC 850C F100K

    CY7B951

    Abstract: G958 PM5345 SY69951 VNS67200 TOOC
    Text: * eV M C O O V OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER SYNERGY SEM IC O N D UC TO R INFORMATION SY69951 DESCRIPTION FEATURES • SONET/SDH and ATM Compatible ■ Seamless operation with PMC-Sierra PM5345 SUN , VTI VNS67200 Quad UNI Processor, IgT WAC-013-B


    OCR Scan     		PDF SY69951 PM5345 VNS67200 WAC-013-B PD98402 52MHz 44MHz 84MHz 48MHz 28-pin CY7B951 G958 SY69951 TOOC

    Untitled

    Abstract: No abstract text available
    Text: Clockworks ADVANCE INFORMATION SY10EL34 SY100EL34 - 2 , ^4, ^ 8 CLOCK SYNERGY GENERATION CHIP SEMICONDUCTOR DESCRIPTION FEATURES 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75Ki2 input pull-down resistors


    OCR Scan     		PDF SY10EL34 SY100EL34 75Ki2 SY10EL/100EL34 OD13Sb SY10EL34ZC SY100EL34ZC

    Untitled

    Abstract: No abstract text available
    Text: * 3-BIT 4:1 MUX-LATCH SYNERGY SY10E156 SY100E156 SEMICONDUCTOR FEATURES DESCRIPTION • ■ ■ ■ ■ ■ ■ dOOps max. D to output Extended 100E V e e range of -4.2V to -5.5V 800ps max. LEN to output Differential outputs Asynchronous Master Reset Dual latch enables


    OCR Scan     		PDF SY10E156 SY100E156 800ps MC10E/100E156 J28-1 SY100E156JCTR SY100E156JC SY10E156JCTR

    sy89429jc

    Abstract: "Z3N" SY89429
    Text: SYNERGY Clockworks PRELIMINARY SY89429 FREQUENCY SYNTHESIZER SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ 25 to 400MHz differential PECL outputs ±25ps output jitter within 100 cycles Minimal frequency over-shoot Synthesized architecture Serial 3 wire interface


    OCR Scan     		PDF PRELISMY89429 bY894< 400MHz 28-pin SY89429 800MHz. T0013A1 00005M7 SY89429 SY89429JC "Z3N"

    Untitled

    Abstract: No abstract text available
    Text: « LOW-POWER OCTAL ECL/TTL BI-DIRECTIONAL TRANSLATOR C V M C D ^V SYNERGY SEMICONDUCTOR PRELIMINARY syioos329 W |T H R E g i s T E R FEATURES DESCRIPTION • Bi-directional translation ■ ESD protection of 2000V ■ ECL high impedance outputs ■ Registered outputs


    OCR Scan     		PDF syioos329 SY100S329DC SY100S329FC D24-1 F24-1

    F100K

    Abstract: SY100S324 SY100S324DC D2418
    Text: * LOW PO W ER HEX TTL-to-E C L TRANSLATO R SYNERGY S E M IC O N D U C T O R FEATURES SY100S324 DESCRIPTION Max. propagation delay of 1,4ns min. of —70mA The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL


    OCR Scan     		PDF SY100S324 F100K D24-1 TD013Ã 0DD21Ã SY100S324DC D24-1 SY100S324FC F24-1 F100K SY100S324 D2418

    SY100S863

    Abstract: SY100S863JC SY100S863JCTR
    Text: ^ V U „ /1 V 8-|NPUT PECL d i f f e r e n t i a l m ux w it h t t l s e l e c t s SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • Low skew ■ Differential PECL inputs ■ Differential cut-off PECL outputs capable of driving 25Q load for driving data bus


    OCR Scan     		PDF SY100S863 SY100S863 T0D13Ã 00022b? SY100S863JC J28-1 SY100S863JCTR

    F100K

    Abstract: SY100S341
    Text: T0013fll « 0002213 3Û0 8-BIT SHIFT REGISTER SYNERGY SY100S341 S E M IC O N D U C T O R FEATURES • ■ Max. shift frequency of 600MHz ■ Max. Clock to Q delay of 1200ps ■ Iee min. of -150m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels


    OCR Scan     		PDF T0013fll SY100S341 600MHz 1200ps -150mA F100K SY100S341 D24-1 F100K

    SY69612

    Abstract: HP 85700A HP53132A
    Text: * SONET/SDH/ATM OC-12 TRANSCEIVER SYNERGY SEMICONDUCTOR FEATURES PRELIMINARY INFORMATION SY69612 DESCRIPTION A complete SONET/SDH Transmitter & Receiver Complies with Bellcore, CCiTT and ANSI specifications On-chip PLL for clock generation SONET framing defeatable


    OCR Scan     		PDF OC-12 SY69612 SY69612 OC-12 84MHz 44MHz) SY87612, STS-12/OC-12 HP 85700A HP53132A