100325PC
Abstract: F100K M24B MO-047 MS-013 N24E V28A 100325QC 100325QI 100325SC
Text: Revised August 2000 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential
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F100K
100325PC
M24B
MO-047
MS-013
N24E
V28A
100325QC
100325QI
100325SC
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DS009879
Abstract: No abstract text available
Text: Revised November 1999 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential
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F100K
DS009879
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100391PC
Abstract: 100391QC 100391QI 100391SC F100K M24B MO-047 MS-013 N24E V28A
Text: Revised August 2000 100391 Low Power Single Supply Hex TTL-to-PECL Translator General Description Features The 100391 is a hex translator for converting TTL logic levels to F100K PECL logic levels. The unique feature of this translator, is the ability to do this translation using only one
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F100K
100391PC
100391QC
100391QI
100391SC
M24B
MO-047
MS-013
N24E
V28A
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100393QC
Abstract: F100K MO-047 V28A
Text: Revised November 1999 100393 Low Power 9-Bit ECL-to-TTL Translator with Latches General Description Features The 100393 is a 9-bit translator for converting F100K logic levels to TTL logic levels. A LOW on the latch enable LE latches the data at the input state. A HIGH on the LE
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F100K
100393QC
MO-047
V28A
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b37 diode
Abstract: C1995 F100K J24E M24B N24E V28A W24B 1380B
Text: 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels Differential inputs allow each circuit to be used as an inverting non-inverting or differential receiver An internal reference voltage generator provides
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F100K
b37 diode
C1995
J24E
M24B
N24E
V28A
W24B
1380B
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F100K
Abstract: No abstract text available
Text: 100397 Quad Differential ECL/TTL Translating Transceiver with Latch General Description The 100397 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability
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F100K
Abstract: L817
Text: F100194 Quint Duplex Bus Driver T ransceiver F100K ECL Product Description The F100194 is a qu in t line driver/receiver capable of transm itting and receiving fu ll duplex digital signals on ; high-speed bus line. Because o f the current source line driver, tw o independent messages may be transm itted
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F100194
F100K
F100194
L817
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Untitled
Abstract: No abstract text available
Text: F100114 Quint Differential Line Receiver FAIRCHILD A Schlumberger Company F100K ECL Product Description The F100114 is a m on o lith ic q u in t differential line receiver w ith em itte r-fo llo w e r outputs. An internal reference supply V b b is available fo r single-ended
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F100114
F100K
F100114
24-Pin
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Untitled
Abstract: No abstract text available
Text: * SYNERGY LOW-POWER HEX TTL-TO-PECL TRANSLATOR SY100S391 SEMICONDUCTOR DESCRIPTION FEATURES Operates from a single +5V supply Differential PECL outputs Companion chip to SY100S390 PECL-to-TTL translator Function and pinout compatible with National and Signetics F100K
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SY100S391
SY100S390
F100K
24-pin
28-pin
SY100S391
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333 045 01
Abstract: No abstract text available
Text: FAIRCHILD F 100122 A S chlum berger C om pari' ^ ^ ÎU ff l* F100K ECL Product Connection Diagrams Description The F100122 is a m on o lith ic 9-bit buffer. The device contains nine non-inverting buffer gates with single input and output. All inputs have 50 k i! pull-dow n
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F100K
F100122
24-Pin
F1001
333 045 01
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Untitled
Abstract: No abstract text available
Text: F100165 Universal Priority Encoder FAIRCHILD A Schlumberger Company F100K ECL Product Description The F100165 contains eight input latches w ith a com m on Enable E follow ed by encoding logic w hich generates the binary address of the highest p rio rity input
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F100165
F100K
24-Pin
F100165
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Untitled
Abstract: No abstract text available
Text: F100170 Universal Demultiplexer/ Decoder FAIRCHILD A S c h lu m b e rg e r C o m p a n y F100K ECL Product Description The F100170 universal dem ultiplexer/decoder functions as either a dual 1-of-4 decoder or as a single 1-of-8 decoder, depending on the signal applied to the M ode
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F100170
F100K
24-Pin
F100170
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Untitled
Abstract: No abstract text available
Text: S E M IC O N D U C T O R tm 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex tra n sla tor fo r converting F100K logic levels to T T L logic levels. D ifferential inputs allo w each circuit to be used as an inverting, non-inverting or differential re
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F100K
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7AC8
Abstract: No abstract text available
Text: F10474 1024 x 4-Bit Static Random Access Memory FA IR C H ILD A S chlum berger C om pany F100K ECL Product Description The F10474 is a 4096-bit read/w rite Random Access M em ory RAM , organized 1024 w ords by fo u r bits per w ord. It is designed for high-speed scratchpad, control
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F10474
F100K
24-Pin
4096-bit
F10474
7AC8
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Untitled
Abstract: No abstract text available
Text: F100474 1024 x 4-Bit Static Random Access Memory FAIRCHILD A Schlumberger Company F100K ECL Product Description The F100474 is a 4096-bit read/w rite Random Access M em ory R AM , organized 1024 w ords by fo u r bits per w ord. It is designed fo r high-speed scratchpad, control
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F100474
F100K
24-Pin
4096-bit
F100474
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m3ub
Abstract: F100160
Text: F100160 Dual Parity Checker/Generator FAIRCHILD S c h lu m b e rg e r C o m p a n y A F100K ECL Product Connection Diagrams Description The F100160 is a dual parity checker/generator. Each half has nine inputs; the o utput is HIG H when an even num ber of inputs are HIGH. One of the nine inputs la or
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F100160
F100K
24-Pin
F100160
m3ub
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Untitled
Abstract: No abstract text available
Text: F A A I R C H I L F100150 Hex D Latch D S chlum berger C om pany F100K ECL Product Description The F100150 contains six D-type latches with true and com p le m e nt outputs, a pair o f C om m on Enables ~Ea and Eb , and a com m on Master Reset (MR). A Q output
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F100K
24-Pin
F100150
F100150
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Untitled
Abstract: No abstract text available
Text: F100181 4-BIT BINARY/BCD ALU F100K SERIES ECL DESCRIPTION - The F100181 performs eight logic operations and eight arithmetic op-j. erations on a pair of 4-bit words. The operating mode is determined by signals appliejjIJojJ the Select Sn inputs, as shown in the Function Select table. In addition to per1—
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F100181
F100K
F100181
look90
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PN generator circuit
Abstract: No abstract text available
Text: F100141 8-Bit Shift Register F100K ECL Product Connection Diagrams Description The F100141 contains eight edge-triggered, D-type flip-flops with individual inputs Pn and outputs (Qn) for parallel operation, and with serial inputs (D n) and steering logic for bidirectional shifting. The flip-flops
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F100141
F100K
F100141
24-Pin
PN generator circuit
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ODC4
Abstract: F100107
Text: F100107 Quint Exclusive OR/NOR Gate F100K ECL Product Description The F100107 is a monolithic quint exclusive-OR/NOR gate. The Function output is the wire-OR of all five exclusive-OR outputs: F = D1a D2a + (D1b D 2b) + (Di c © D 2c) + (D1d© D2d) + (D1e© D2e).
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F100107
F100K
24-Pin
F100107
ODC4
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F100102DC
Abstract: No abstract text available
Text: F100102 Quint 2-Input OR/NOR Gate F100K ECL Product Connection Diagrams Description The F100102 is a monolithic quint 2-input OR/NOR gate with common enable. Ail inputs have 50 kO pull-down resistors and all outputs are buffered. Pin Names Dna- Dne E O a-O e
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F100102
F100K
24-Pin
F100102
F100102DC
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F100325
Abstract: F100125 F100K
Text: 100125 5251 N a tio n a l w im S e m ic o n d u c to r F100125 Hex ECL-to-TTL Translator General Description The F100125 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each cir cuit to be used as an inverting, non-inverting or differential
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F100125
F100125
F100K
tl/f/9849-5
500il
tl/f/9849-6
F100325
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DIODE OA90
Abstract: OA90 diode eel -16-2005 F100K V28A
Text: EM ICDNDUCTOR t 100393 Low Power 9-Bit ECL-to-TTL Translator with Latches General Description Features The 100393 is a 9 -bit translator fo r converting F100K logic levels to FAST T T L logic levels. A LO W on the latch enable LE latches the d ata at the input state. A HIGH on the LE
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F100K
DIODE OA90
OA90 diode
eel -16-2005
V28A
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100395QC
Abstract: F100K MO-047 V28A
Text: SEMICONDUCTOR Revised N ovem ber 1999 TM 100395 Low Power 9-Bit ECL-to-TTL Translator with Registers General Description Features The 100395 is a 9-bit translator for converting F100K logic levels to T T L logic levels. A HIGH on the output enable OE holds the T T L outputs in a high im pedance state. Two
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F100K
100395QC
MO-047
V28A
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