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    SN74LVC112 Search Results

    SN74LVC112 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LVC112APW Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-TSSOP -40 to 125 Visit Texas Instruments Buy
    SN74LVC112AD Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SOIC -40 to 125 Visit Texas Instruments Buy
    SN74LVC112ADR Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SOIC -40 to 125 Visit Texas Instruments Buy
    SN74LVC112ANSR Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SO -40 to 125 Visit Texas Instruments Buy
    SN74LVC112APWT Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-TSSOP -40 to 125 Visit Texas Instruments Buy
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    SN74LVC112 Price and Stock

    Texas Instruments SN74LVC112APWR

    IC FF JK TYPE DUAL 1BIT 16TSSOP
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    DigiKey SN74LVC112APWR Cut Tape 3,132 1
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    SN74LVC112APWR Digi-Reel 3,132 1
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    Mouser Electronics SN74LVC112APWR 7,548
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    Quest Components SN74LVC112APWR 1,120
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    Rochester Electronics SN74LVC112APWR 3,140 1
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    Ameya Holding Limited SN74LVC112APWR 2,000
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    Chip1Stop SN74LVC112APWR Cut Tape 1,893
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    Win Source Electronics SN74LVC112APWR 8,900
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    Texas Instruments SN74LVC112ADR

    IC FF JK TYPE DUAL 1BIT 16SOIC
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    DigiKey SN74LVC112ADR Digi-Reel 2,484 1
    • 1 $0.62
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    SN74LVC112ADR Cut Tape 2,484 1
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    Mouser Electronics SN74LVC112ADR 7,154
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    Bristol Electronics SN74LVC112ADR 2,088
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    Quest Components SN74LVC112ADR 9,500
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    SN74LVC112ADR 1,670
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    Rochester Electronics SN74LVC112ADR 7,500 1
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    Texas Instruments SN74LVC112ADBR

    IC FF JK TYPE DUAL 1BIT 16SSOP
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    DigiKey SN74LVC112ADBR Digi-Reel 1,995 1
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    SN74LVC112ADBR Cut Tape 1,995 1
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    Mouser Electronics SN74LVC112ADBR
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    Rochester Electronics SN74LVC112ADBR 61,570 1
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    Texas Instruments SN74LVC112ADGVR

    IC FF JK TYPE DUAL 1BIT 16TVSOP
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    DigiKey SN74LVC112ADGVR Cut Tape 1,491 1
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    SN74LVC112ADGVR Digi-Reel 1,491 1
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    Mouser Electronics SN74LVC112ADGVR 4,621
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    Rochester Electronics SN74LVC112ADGVR 82,000 1
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    Texas Instruments SN74LVC112APWT

    IC FF JK TYPE DUAL 1BIT 16TSSOP
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    DigiKey SN74LVC112APWT Cut Tape 812 1
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    SN74LVC112APWT Digi-Reel 812 1
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    Mouser Electronics SN74LVC112APWT
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    Rochester Electronics SN74LVC112APWT 32,159 1
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    Win Source Electronics SN74LVC112APWT 8,958
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    Find more SN74LVC112 price and stock on Findchips.com

    SN74LVC112 Datasheets (116)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    SN74LVC112A Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset Original PDF
    SN74LVC112A Texas Instruments DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Original PDF
    SN74LVC112A Texas Instruments DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Original PDF
    SN74LVC112AD Texas Instruments SN74LVC112 - Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SOIC -40 to 85 Original PDF
    SN74LVC112AD Texas Instruments Logic - Flip Flops, Integrated Circuits (ICs), IC JK TYPE NEG TRG DUAL 16SOIC Original PDF
    SN74LVC112AD Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SOIC -40 to 85 Original PDF
    SN74LVC112AD Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop with Clear and Preset Original PDF
    SN74LVC112AD Texas Instruments DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Original PDF
    SN74LVC112ADB Texas Instruments DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Original PDF
    SN74LVC112ADBLE Texas Instruments SN74LVC112 - Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SSOP -40 to 85 Original PDF
    SN74LVC112ADBLE Texas Instruments DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Original PDF
    SN74LVC112ADBLE Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SSOP -40 to 85 Original PDF
    SN74LVC112ADBR Texas Instruments SN74LVC112 - Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SSOP -40 to 85 Original PDF
    SN74LVC112ADBR Texas Instruments Logic - Flip Flops, Integrated Circuits (ICs), IC JK TYPE NEG TRG DUAL 16SSOP Original PDF
    SN74LVC112ADBR Texas Instruments DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET Original PDF
    SN74LVC112ADBR Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SSOP -40 to 85 Original PDF
    SN74LVC112ADBR Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop with Clear and Preset Original PDF
    SN74LVC112ADBRE4 Texas Instruments Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SSOP -40 to 85 Original PDF
    SN74LVC112ADBRE4 Texas Instruments DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR and PRESET Original PDF
    SN74LVC112ADBRE4 Texas Instruments SN74LVC112 - Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SSOP -40 to 85 Original PDF

    SN74LVC112 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A) SNS74LVC2G53 scyb014 scyb005 scym001

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    LCV112A

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289I – JANUARY 1993 – REVISED MARCH 2002 D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Inputs Accept Voltages to 5.5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN74LVC112A SCAS289I 000-V A114-A) A115-A) LCV112A

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    LC112A

    Abstract: LVC112A A115-A C101 SN74LVC112A SN74LVC112AD
    Text: SN74LVC112A DUAL NEGATIVEĆEDGEĆTRIGGERED JĆK FLIPĆFLOP WITH CLEAR AND PRESET SCAS289K − JANUARY 1993 − REVISED OCTOBER 2003 D D D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.8 ns at 3.3 V


    Original     		PDF SN74LVC112A SCAS289K 000-V A114-A) A115-A) LC112A LVC112A A115-A C101 SN74LVC112A SN74LVC112AD

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    A115-A

    Abstract: C101 SN74LVC112A SN74LVC112AD LC112 CPD14
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A) A115-A C101 SN74LVC112A SN74LVC112AD LC112 CPD14

    SN74LVC112A

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289H – JANUARY 1993 – REVISED JUNE 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN74LVC112A SCAS289H MIL-STD-883, SN74LVC112A

    SN74LVC112A

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289B – JANUARY 1993 – REVISED SEPTEMBER 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN74LVC112A SCAS289B SN74LVC112A

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    A115-A

    Abstract: C101 SN74LVC112A SN74LVC112AD LC112A
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289K – JANUARY 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289K 000-V A114-A) A115-A) A115-A C101 SN74LVC112A SN74LVC112AD LC112A

    SN74LVC112A

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289D – JANUARY 1993 – REVISED JANUARY 1997 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V


    Original     		PDF SN74LVC112A SCAS289D MIL-STD-883, JESD-17 SN74LVC112A

    A115-A

    Abstract: C101 SN74LVC112A SN74LVC112AD LC112A
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289J – JANUARY 1993 – REVISED AUGUST 2002 D D D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.8 ns at 3.3 V


    Original     		PDF SN74LVC112A SCAS289J 000-V A114-A) A115-A) A115-A C101 SN74LVC112A SN74LVC112AD LC112A

    LC112A

    Abstract: A115-A C101 SN74LVC112A SN74LVC112AD
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A) LC112A A115-A C101 SN74LVC112A SN74LVC112AD

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET _ SCAS28BA-JANUARY 1 9 9 3 - REVISED JULY 1995 EPIC Enhanced-Performance Implanted CMOS Submicron Process D, DB, OR PW PACKAGE (TOP VIEW) Typical V q l p (Output Ground Bounce)


    OCR Scan     		PDF SN74LVC112 SCAS28BA-JANUARY

    H723

    Abstract: No abstract text available
    Text: SN74LVC112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289 - JANUARY 1993 - REVISED MARCH 1994 EPIC Enhanced-Performance Implanted CMOS S'übmicron Process Typical V q lp (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C


    OCR Scan     		PDF SN74LVC112 SCAS289 -100MA IOH--12mA H723

    SN74LVC112A

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET S C AS 289E - JA N U A R Y 1993 - R EVISED JA N U A R Y 1998 D EPIC Enhanced-Performance Implanted CMOS Submicron Process D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V


    OCR Scan     		PDF SN74LVC112A SCAS289E MIL-STD-883, 10MHz, SN74LVC112A

    Untitled

    Abstract: No abstract text available
    Text: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED Ü-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289E - JANUARY 1 9 9 3 - REVISED JANUARY 1996 • • • • "IToIfo R PACKAGE TOP VIEW EPICrM(Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per


    OCR Scan     		PDF SN74LVC112A SCAS289E MIL-STD-883, JESD17

    SM 7525

    Abstract: 74LVC112
    Text: SN74LVC112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET S C A S 2 8 9 -J A N U A R Y 1 9 9 3 - REVISED M ARCH 1994 , DB, OR PW PACKAGE TOP VIEW E P IC (Enhanced-Perform ance Implanted CM OS) Subm icron P rocess Typical V q l p (Output G round Bounce)


    OCR Scan     		PDF SN74LVC112 11CLR SM 7525 74LVC112

    SN74LVC112

    Abstract: No abstract text available
    Text: SN74LVC112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET JANUARY 1993 • Space-Saving Package Option: Shrink Small-Outline Package DB Features EIAJ 0.65-mm Lead Pitch DB, DW, OR PW PACKAGE (TOP VIEW) • EPIC (Enhanced-Performance Implanted


    OCR Scan     		PDF SN74LVC112 65-mm