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    LVC112A Search Results

    LVC112A Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    LVC112AU Renesas Electronics Corporation QUAD DUAL NEG EDGE FLIP F Visit Renesas Electronics Corporation
    74LVC112APY8 Renesas Electronics Corporation QUAD DUAL NEG EDGE FLIP F Visit Renesas Electronics Corporation
    74LVC112AQ Renesas Electronics Corporation QUAD DUAL NEG EDGE FLIP F Visit Renesas Electronics Corporation
    74LVC112APG Renesas Electronics Corporation QUAD DUAL NEG EDGE FLIP F Visit Renesas Electronics Corporation
    74LVC112APG8 Renesas Electronics Corporation QUAD DUAL NEG EDGE FLIP F Visit Renesas Electronics Corporation
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    LVC112A Price and Stock

    Rochester Electronics LLC SN74LVC112APWR

    SN74LVC112A DUAL NEGATIVE-EDGE-T
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    DigiKey SN74LVC112APWR Bulk 3,140 1,154
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    • 10000 $0.26
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    Texas Instruments SN74LVC112APWR

    IC FF JK TYPE DUAL 1BIT 16TSSOP
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    DigiKey SN74LVC112APWR Cut Tape 2,644 1
    • 1 $0.7
    • 10 $0.616
    • 100 $0.472
    • 1000 $0.29852
    • 10000 $0.29852
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    SN74LVC112APWR Reel 2,000 2,000
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    • 10000 $0.24255
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    Mouser Electronics SN74LVC112APWR 7,597
    • 1 $0.7
    • 10 $0.578
    • 100 $0.438
    • 1000 $0.299
    • 10000 $0.242
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    Rochester Electronics SN74LVC112APWR 3,140 1
    • 1 $0.2625
    • 10 $0.2625
    • 100 $0.2468
    • 1000 $0.2231
    • 10000 $0.2231
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    Ameya Holding Limited SN74LVC112APWR 2,000
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    Chip1Stop SN74LVC112APWR Cut Tape 1,901
    • 1 -
    • 10 $0.464
    • 100 $0.352
    • 1000 $0.282
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    Texas Instruments SN74LVC112ADR

    IC FF JK TYPE DUAL 1BIT 16SOIC
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    DigiKey SN74LVC112ADR Cut Tape 2,484 1
    • 1 $0.74
    • 10 $0.653
    • 100 $0.5008
    • 1000 $0.31674
    • 10000 $0.31674
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    SN74LVC112ADR Digi-Reel 1
    • 1 $0.74
    • 10 $0.653
    • 100 $0.5008
    • 1000 $0.31674
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    Mouser Electronics SN74LVC112ADR 7,235
    • 1 $0.63
    • 10 $0.543
    • 100 $0.417
    • 1000 $0.264
    • 10000 $0.203
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    Bristol Electronics SN74LVC112ADR 2,088
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    Rochester Electronics SN74LVC112ADR 125,422 1
    • 1 $0.2377
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    • 100 $0.2234
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    South Electronics SN74LVC112ADR
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    Texas Instruments SN74LVC112ANSR

    IC FF JK TYPE DUAL 1BIT 16SO
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    DigiKey SN74LVC112ANSR Reel 2,000 2,000
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    Mouser Electronics SN74LVC112ANSR 1,698
    • 1 $0.93
    • 10 $0.767
    • 100 $0.581
    • 1000 $0.396
    • 10000 $0.32
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    Bristol Electronics SN74LVC112ANSR 1,757
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    Texas Instruments SN74LVC112ADBR

    IC FF JK TYPE DUAL 1BIT 16SSOP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LVC112ADBR Reel 2,000 2,000
    • 1 -
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    • 10000 $0.28361
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    Mouser Electronics SN74LVC112ADBR
    • 1 $0.79
    • 10 $0.656
    • 100 $0.503
    • 1000 $0.35
    • 10000 $0.279
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    Rochester Electronics SN74LVC112ADBR 77,570 1
    • 1 $0.315
    • 10 $0.315
    • 100 $0.2961
    • 1000 $0.2677
    • 10000 $0.2677
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    South Electronics SN74LVC112ADBR
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    Find more LVC112A price and stock on Findchips.com

    LVC112A Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A) SNS74LVC2G53 scyb014 scyb005 scym001

    Untitled

    Abstract: No abstract text available
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    msi 7267 MOTHERBOARD SERVICE MANUAL

    Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
    Text: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information


    Original     		PDF GDFP1-F48 -146AA GDFP1-F56 -146AB msi 7267 MOTHERBOARD SERVICE MANUAL ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555

    LCV112A

    Abstract: No abstract text available
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289I – JANUARY 1993 – REVISED MARCH 2002 D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Inputs Accept Voltages to 5.5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C


    Original     		PDF SN74LVC112A SCAS289I 000-V A114-A) A115-A) LCV112A

    Untitled

    Abstract: No abstract text available
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    LC112A

    Abstract: LVC112A A115-A C101 SN74LVC112A SN74LVC112AD
    Text: LVC112A DUAL NEGATIVEĆEDGEĆTRIGGERED JĆK FLIPĆFLOP WITH CLEAR AND PRESET SCAS289K − JANUARY 1993 − REVISED OCTOBER 2003 D D D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.8 ns at 3.3 V


    Original     		PDF SN74LVC112A SCAS289K 000-V A114-A) A115-A) LC112A LVC112A A115-A C101 SN74LVC112A SN74LVC112AD

    Untitled

    Abstract: No abstract text available
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    A115-A

    Abstract: C101 SN74LVC112A SN74LVC112AD LC112 CPD14
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A) A115-A C101 SN74LVC112A SN74LVC112AD LC112 CPD14

    Untitled

    Abstract: No abstract text available
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    A115-A

    Abstract: C101 SN74LVC112A SN74LVC112AD LC112A
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289K – JANUARY 1993 – REVISED FEBRUARY 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289K 000-V A114-A) A115-A) A115-A C101 SN74LVC112A SN74LVC112AD LC112A

    Untitled

    Abstract: No abstract text available
    Text: LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology


    Original     		PDF IDT74LVC112A MIL-STD-883, 200pF,

    LVC112A

    Abstract: IDT74LVC112A
    Text: LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS DUAL LVC112A NEGATIVE-EDGE-TRIGGERED ADVANCE J-K FLIP-FLOP WITH CLEAR INFORMATION AND PRESET, 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION:


    Original     		PDF IDT74LVC112A MIL-STD-883, 200pF, 635mm SO16-7) SO16-8) SO16-9) SO16-10) LVC112A IDT74LVC112A

    A115-A

    Abstract: C101 SN74LVC112A SN74LVC112AD LC112A
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289J – JANUARY 1993 – REVISED AUGUST 2002 D D D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.8 ns at 3.3 V


    Original     		PDF SN74LVC112A SCAS289J 000-V A114-A) A115-A) A115-A C101 SN74LVC112A SN74LVC112AD LC112A

    IDT74LVC112A

    Abstract: LVC112A
    Text: LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS DUAL LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: DESCRIPTION: – – 0.5 MICRON CMOS Technology


    Original     		PDF IDT74LVC112A MIL-STD-883, 200pF, 635mm SO16-7) SO16-8) SO16-9) SO16-10) IDT74LVC112A LVC112A

    LC112A

    Abstract: A115-A C101 SN74LVC112A SN74LVC112AD
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A) LC112A A115-A C101 SN74LVC112A SN74LVC112AD

    8 way flip-flop ic

    Abstract: IDT74LVC112A LVC112A
    Text: LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: This dual negative-edge-triggered J-K flip-flop is built using advanced


    Original     		PDF IDT74LVC112A 8 way flip-flop ic IDT74LVC112A LVC112A

    10KACN

    Abstract: LVC112A EN-4088Z SN74LVC112AD
    Text: TEXAS INSTRUMENTS Final Notification for the Manufacture of SOIC Narrow Body D and SSOP (DL) in all pin variations to TI Mexico Assembly/Test Facility (TMX) December 3, 1997 Abstract Texas Instruments Standard Linear and Logic (SLL) has completed the move of the SOIC and


    Original     		PDF SN74ABT16823DL 5297B 10KACN LVC112A EN-4088Z SN74LVC112AD

    Untitled

    Abstract: No abstract text available
    Text: LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V


    Original     		PDF SN74LVC112A SCAS289L 000-V A114-A) A115-A)

    Untitled

    Abstract: No abstract text available
    Text: 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.635mm pitch QSOP,


    OCR Scan     		PDF IDT74LVC112A MIL-STD-883, 200pF, 635mm LVC112A: voltaVC112A S016-8) S016-9) S016-10) 2975StenderWay

    Untitled

    Abstract: No abstract text available
    Text: 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.635mm pitch QSOP,


    OCR Scan     		PDF MIL-STD-883, 200pF, 635mm LVC112A: S016-8) S016-9) S016-10) 2975StenderWay

    Untitled

    Abstract: No abstract text available
    Text: 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: - DESCRIPTION: 0 .5 M IC R O N C M O S T e c h n o lo g y E S D > 2 0 0 0 V p e r M IL -S T D -8 8 3 , M e th o d 301 5; > 2 0 0 V u s in g m a c h in e m o d e l C = 2 0 0 p F , R = 0


    OCR Scan     		PDF tPLH11 IDT74LVC112A