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    10145226-0241Q13LF Amphenol Communications Solutions DDR4 DIMM, Storage and Server Connector, Vertical , Through Hole, 288 Position , 0.85mm (0.033in) Pitch Visit Amphenol Communications Solutions
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    Amphenol Communications Solutions 10145226-0241Q13LF

    DDR4 288P TH ASSY
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    Amphenol Communications Solutions 10141972-1241Q13LF

    DDR4 288P TH ASSY
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    Q13L Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    70P3337

    Abstract: 70P3307
    Text: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Separate, Independent Read and Write Data Ports


    Original     		PDF IDT70P3307 IDT70P3337 1024K/512K 1024K 233MHz, 250MHz 18/9Mb IDT70P3307/70P3337 70P3337 70P3307

    TAA 611 T12

    Abstract: x48 chipset IDT72T6360 IDT72T6480 D25N3
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb BB324) 72T6480 drw45 TAA 611 T12 x48 chipset IDT72T6360 IDT72T6480 D25N3

    Untitled

    Abstract: No abstract text available
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb BB324) 72T6360

    Untitled

    Abstract: No abstract text available
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb BB324) 72T6480 drw45

    TAA 611 T12

    Abstract: 72T6480 BA1-B11 d25n3 BA0-C11 k4h561638f A11-C10 q35t Q35T1 A7D9
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb drw44 BB324) 72T6480 drw45 TAA 611 T12 72T6480 BA1-B11 d25n3 BA0-C11 k4h561638f A11-C10 q35t Q35T1 A7D9

    Q13L

    Abstract: 70P3337 CQX 89 IDT70P3307 IDT70P3337 diode d5r 70P3307
    Text: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Separate, Independent Read and Write Data Ports


    Original     		PDF IDT70P3307 IDT70P3337 1024K/512K 1024K 233MHz, 250MHz de024 70P3337 drw17 Q13L CQX 89 IDT70P3307 IDT70P3337 diode d5r 70P3307

    72T6480

    Abstract: dsc-6358 IDT72T6360 IDT72T6480 D2312
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb 133MHz IDT72T6480 x48in x48out x24out x12out 72T6480 dsc-6358 IDT72T6360 IDT72T6480 D2312

    70P35

    Abstract: 70P3517
    Text: PRELIMINARY DATASHET IDT70P3537 IDT70P3517 512K/256K x36 SYNCHRONOUS DUAL QDR-IITM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density 512K x 36 – Also available 9Mb Density (256K x 36) QDR-II x 36 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Two independent ports


    Original     		PDF IDT70P3537 IDT70P3517 512K/256K 233MHz, 250MHz 18/9Mb IDT70P3537/70P3517 70P35 70P3517

    CQX 89

    Abstract: DIODE Q20L Q33R Q19L Q23R d27l doff IDT70P3537 IDT70P3517 Q13R
    Text: PRELIMINARY DATASHET IDT70P3537 IDT70P3517 512K/256K x36 SYNCHRONOUS DUAL QDR-IITM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density 512K x 36 – Also available 9Mb Density (256K x 36) QDR-II x 36 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Two independent ports


    Original     		PDF IDT70P3537 IDT70P3517 512K/256K 233MHz, 250MHz 18/9Mb IDT70P3537/70P3517 CQX 89 DIODE Q20L Q33R Q19L Q23R d27l doff IDT70P3537 IDT70P3517 Q13R

    IDT72T6360

    Abstract: IDT72T6480 2x16Mb
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb BB324) 72T6360 IDT72T6360 IDT72T6480 2x16Mb

    72T63

    Abstract: No abstract text available
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb BB324) 72T6360 72T63

    72T63

    Abstract: No abstract text available
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb 166MHz IDT72T6360 x36in x36out x18out x18in 72T63

    Q11L

    Abstract: 70P3337 CQX 89 IDT70P3307 IDT70P3337 RM-576 Q15L tbl17 BW1R q11r
    Text: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz


    Original     		PDF IDT70P3307 IDT70P3337 1024K/512K 1024K 233MHz, 250MHz 18/9Mb IDT70P3307/70P3337 Q11L 70P3337 CQX 89 IDT70P3307 IDT70P3337 RM-576 Q15L tbl17 BW1R q11r

    DIODE Q20L

    Abstract: D34l IDT70P3517 Q21L CQX 89 IDT70P3537 Q20L D34R Q26R Q11L
    Text: PRELIMINARY DATASHET IDT70P3537 IDT70P3517 512K/256K x36 SYNCHRONOUS DUAL QDR-IITM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density 512K x 36 – Also available 9Mb Density (256K x 36) QDR-II x 36 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Two independent ports


    Original     		PDF IDT70P3537 IDT70P3517 512K/256K 233MHz, 250MHz 70P3517 drw17 DIODE Q20L D34l IDT70P3517 Q21L CQX 89 IDT70P3537 Q20L D34R Q26R Q11L

    TAA 611 T12

    Abstract: A6C9 128M DDR SDR SDRAM samsung 0 IDT72T6360 IDT72T6480
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb BB324) 72T6480 drw45 TAA 611 T12 A6C9 128M DDR SDR SDRAM samsung 0 IDT72T6360 IDT72T6480

    TAA 611 T12

    Abstract: 17x18 BA0-C11 DQ51d DQ34-C12
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb IDT72T6360 BB324) 72T6360 TAA 611 T12 17x18 BA0-C11 DQ51d DQ34-C12

    Untitled

    Abstract: No abstract text available
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb BB324) 72T6480 drw45

    TAA 611 T12

    Abstract: IDT72T6360 IDT72T6480
    Text: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag


    Original     		PDF 128Mb 256Mb BB324) 72T6360 TAA 611 T12 IDT72T6360 IDT72T6480

    s 15018

    Abstract: No abstract text available
    Text: N T E ELECTRONIC?; TNC_ ¿ s e ]> • b 4 3 1 5 S ci 0 0 0 5 7 0 3 2bb H N T E T -S # 'O l POSITIVE, 3 TERMINAL, ARRANGED BY OUTPUT VOLTAGE Vottag* n Regulated Voltage Out ±5% Volti) KTEfype Number Cm * Styl« (Vo«*) Diagram Number V«ui V* Hu urn


    OCR Scan     		PDF 1934X T0220 Diagram414 s 15018

    Untitled

    Abstract: No abstract text available
    Text: [ p fô iiy o » « ? in t e i M82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS High Performance 32-Bit DMA Controller — 40 Mbytes/sec Maximum Data Transfer Rate at 20 MHz — 8 Independently Programmable Channels


    OCR Scan     		PDF M82380 32-BIT 20-Source M8259A 16-Bit M82C54 132-Pin 164-Pin 2bl75

    Untitled

    Abstract: No abstract text available
    Text: SONY CXD2409R Timing Controller for ICX076/077AL Description The CXD2409R is a timing controller for CCD camera systems which use the ICX076/077AL black-and-white CCD image sensors. Features • Supports EIA/CCIR standards • Electronic iris electronic shutter function


    OCR Scan     		PDF CXD2409R ICX076/077AL CXD2409R 074ns A3fl23fl3

    MSC1150

    Abstract: Q18c msc1150m Q2SC MSC1150RS
    Text: OKI semiconductor MSC1150 / MSC1171/ MSC1173 Under development 10-bit/20-bit/32-bit ANODE/GRID DRIVER GENERAL DESCRIPTION T h e M S C 1 1 5 0 / M S C 1 1 7 1 / M S C 1 1 7 3 a r e v a c u u m f lu o r e s c e n t d is p la y d r iv e r IC s w h ic h c o n s is t o f s h ift


    OCR Scan     		PDF MSC1150 MSC1171/ MSC1173 10-bit/20-bit/32-bit Q18c msc1150m Q2SC MSC1150RS

    ILO75

    Abstract: No abstract text available
    Text: fax id: 5215 CYPRESS CY7C027V/028V CY7C037V/038V PRELIMINARY 3.3V 32K/64KX 16/18 Dual-Port Static RAM Features • Fully asynchronous operation • Automatic power-down • Expandable data bus to 32/36 bits or more using Mas­ ter/Slave chip select when using more than one device


    OCR Scan     		PDF CY7C027V/028V CY7C037V/038V 32K/64KX CY7C027V) CY7C028V) CY7C037V) CY7C038V) 35-micron 100-Pin ILO75