SMR 40000c
Abstract: MMC760 la 4763 AT91CAP7 AT91CAP9 AT24LC toshiba NAND Flash memory controller ecc 6264B k 2996 4b1 toshiba
Text: Features • Incorporates the ARM926EJ-S ARM Thumb® Processor • • • • • • • • • • – DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz
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ARM926EJ-STM
6264B
26-Nov-07
SMR 40000c
MMC760
la 4763
AT91CAP7
AT91CAP9
AT24LC
toshiba NAND Flash memory controller ecc
k 2996
4b1 toshiba
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R/marvell ethernet switch mi
Abstract: marvell alaska program interface Marvell PXA168
Text: Specification Update Marvell ARMADA 16x Applications Processor Family ARMADA 160, 162, 166 and 168 Products 1. Introduction This document contains updates to the specifications for the Marvell® ARMADA 16x Applications Processor Family. This document is a compilation of device and documentation errata, specification clarifications, and specification changes. It is
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MV-S501140-00
R/marvell ethernet switch mi
marvell alaska program interface
Marvell PXA168
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LED DRIVER ana 618
Abstract: AT91CAP9 6264C ET 439 AC97 ARM926EJ-S AT91CAP9S250A AT91CAP9S500A ISO7816 k 3878
Text: Features • Incorporates the ARM926EJ-S ARM Thumb® Processor • • • • • • • • • • – DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz
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ARM926EJ-STM
6264C
24-Mar-09
LED DRIVER ana 618
AT91CAP9
ET 439
AC97
ARM926EJ-S
AT91CAP9S250A
AT91CAP9S500A
ISO7816
k 3878
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Untitled
Abstract: No abstract text available
Text: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/ Document Title 512MBit 4Bank x 4M x 32bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - Initial Draft Sep.2006 Preliminary 0.2 - Added SRR function and timing diagram Jan.2007
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512Mbit
512MBit
32bits)
LPDDR333
32bit)
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LPDDR200
Abstract: HY5MS7B6BLFP
Text: 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Document Title 512Mbit 4Bank x 8M x 16bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - Initial Draft Sep.2006 Preliminary 0.2 - Added SRR function and timing diagram
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512Mbit
512Mbit
16bits)
LPDDR266
16bit)
00Typ.
LPDDR200
HY5MS7B6BLFP
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AT91CAP9
Abstract: IC BOSCH spi 4254 FM TRANSMITTER db broadcast ke 20 user manual Wireless Bluetooth V2.0 Transceiver Module RS232 AT91CAP9S250A
Text: Features • Incorporates the ARM926EJ-S ARM Thumb® Processor • • • • • • • • • • – DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz
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ARM926EJ-STM
Gates/250
21-May-07
AT91CAP9
IC BOSCH spi 4254
FM TRANSMITTER db broadcast ke 20 user manual
Wireless Bluetooth V2.0 Transceiver Module RS232
AT91CAP9S250A
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