H5TQ2G63BFR-H9C
Abstract: H5TQ1G83BFR-H9C H26M42001EFR H5RS1H23MFR h27u1g8f2b H27U1G8F2 H27UBG8T2A H27UBG8T H5MS2G22MFR-J3M H26M54001BKR
Text: Rev 0.0 Q2’2010 Databook C omputing Memory DDR3 SDRAM : Component VDD DENSITY ORG. SPEED PART NUMBER PKG. FEATURE AVAIL. 1.5V 1Gb 256Mx4 DDR3 1333 H5TQ1G43BFR-H9C FBGA 78ball 8Bank, 1.5V, CL9,9-9-9 Now H5TQ1G43TFR-H9C FBGA(78ball) 8Bank, 1.5V, CL9,9-9-9
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Original
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PDF
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256Mx4
H5TQ1G43BFR-H9C
78ball)
H5TQ1G43TFR-H9C
H5TQ1G43BFR-G7C
H5TQ1G43TFR-G7C
H5TQ1G83BFR-H9C
H5TQ2G63BFR-H9C
H5TQ1G83BFR-H9C
H26M42001EFR
H5RS1H23MFR
h27u1g8f2b
H27U1G8F2
H27UBG8T2A
H27UBG8T
H5MS2G22MFR-J3M
H26M54001BKR
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Untitled
Abstract: No abstract text available
Text: 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Document Title 512Mbit 4Bank x 8M x 16bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - Initial Draft Sep.2006 Preliminary 0.2 - Added SRR function and timing diagram
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Original
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PDF
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512Mbit
512Mbit
16bits)
16bit)
00Typ.
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hynix mobile DDR
Abstract: No abstract text available
Text: 512MBit MOBILE DDR SDRAMs based on 8M x 4Bank x16 I/O Document Title 512MBit 4Bank x 8M x 16bits MOBILE DDR SDRAM Memory Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Sep.2006 Preliminary 0.2 Added SRR function and timing diagram
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Original
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PDF
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512MBit
512MBit
16bits)
32Mx16bit)
11Preliminary
00Typ.
hynix mobile DDR
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LPDDR200
Abstract: HY5MS7B6BLFP
Text: 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Document Title 512Mbit 4Bank x 8M x 16bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - Initial Draft Sep.2006 Preliminary 0.2 - Added SRR function and timing diagram
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Original
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PDF
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512Mbit
512Mbit
16bits)
LPDDR266
16bit)
00Typ.
LPDDR200
HY5MS7B6BLFP
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