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    KM48S803 Price and Stock

    Samsung Semiconductor KM48S8030CT-G10

    SDRAM, 8M x 8, 54 Pin, Plastic, TSOP
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    Quest Components KM48S8030CT-G10 128
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    Samsung Semiconductor KM48S8030BT-GH

    SDRAM, 8M x 8, 54 Pin, Plastic, TSOP
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    Quest Components KM48S8030BT-GH 40
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    KM48S803 Datasheets (14)

    Part ECAD Model Manufacturer Description Curated Type PDF
    KM48S8030 Samsung Electronics 2M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S8030C Samsung Electronics 2M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S8030CT-G/F10 Samsung Electronics 2M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S8030CT-G/F7 Samsung Electronics 2M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S8030CT-G/F8 Samsung Electronics 2M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S8030CT-G/FA Samsung Electronics 2M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S8030CT-G/FH Samsung Electronics 2M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S8030CT-G/FL Samsung Electronics 2M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S8030CT-GL Samsung Electronics KM48S8030CT 2M x 8-Bit x 4 Banks Synchronous DRAM Organization = 8Mx8 Bank/ Interface = 4B/LVTTL Refresh = 4K/64ms Speed = 75,80,1H,1L,10 Package = 54TSOP2 Power = C,l Production Status = Eol Comments = - Original PDF
    KM48S8030D Samsung Electronics 64Mbit SDRAM 2M x 8-Bit x 4 Banks Synchronous DRAM LVTTL Original PDF
    KM48S8030DT-G/F8 Samsung Electronics 2M x 8-Bit x 4 banks synchronous DRAM, 3.3V power supply, LVTTL, 125MHz Original PDF
    KM48S8030DT-G/FA Samsung Electronics 2M x 8-Bit x 4 Banks Synchronous DRAM Original PDF
    KM48S8030DT-G/FH Samsung Electronics 2M x 8-Bit x 4 banks synchronous DRAM, 3.3V power supply, LVTTL, 100MHz Original PDF
    KM48S8030DT-G/FL Samsung Electronics 2M x 8-Bit x 4 Banks Synchronous DRAM Original PDF

    KM48S803 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    KM48S8030BT

    Abstract: No abstract text available
    Text: KM48S8030B CMOS SDRAM Revision History Revision .3 November 1997 - tRDL has changed 10ns to 12ns. - Binning -10 does not meet PC100 characteristics . So AC parameter/Characteristics have changed to 64M 2nd values. Revision .4 (February 1998) - Input leakage Currents (Inputs / DQ) are changed.


    Original     		PDF KM48S8030B PC100 KM48S8030BT

    KM48S8030D

    Abstract: No abstract text available
    Text: KM48S8030D CMOS SDRAM 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 May 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 May 1999 KM48S8030D CMOS SDRAM Revision History Revision 0.0 May 15, 1999


    Original     		PDF KM48S8030D 64Mbit A10/AP KM48S8030D

    16MX4

    Abstract: KMM390S823DT1-GA samsung note
    Text: SERIAL PRESENCE DETECT PC133 Registered DIMM Registered SDRAM PC133 DIMM 168pin SPD Specification REV. 1 July. 1999 REV. 1 July. '99 SERIAL PRESENCE DETECT PC133 Registered DIMM KMM390S823DT1-GA •Organization : 8MX72 •Composition : 8MX8 *9 •Used component part # : KM48S8030DT-GA


    Original     		PDF PC133 168pin) KMM390S823DT1-GA 8MX72 KM48S8030DT-GA 4K/64ms 128bytes 256bytes 16MX4 KMM390S823DT1-GA samsung note

    KM48S8030BT

    Abstract: No abstract text available
    Text: KM48S8030B CMOS SDRAM Revision History Revision .3 November 1997 - tRDL has changed 10ns to 12ns. - Binning -10 does not meet PC100 characteristics . So AC parameter/Characteristics have changed to 64M 2nd values. Revision .4 (February 1998) - Input leakage Currents (Inputs / DQ) are changed.


    Original     		PDF KM48S8030B PC100 A10/AP KM48S8030BT

    KM48S8030C

    Abstract: No abstract text available
    Text: KM48S8030C Preliminary CMOS SDRAM Revision History Revision 1 May 1998 - ICC2N value (10mA) is changed to 12mA. Revision .2 (June 1998) - tSH (-10 binning) is revised. REV. 2 June '98 Preliminary CMOS SDRAM KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM


    Original     		PDF KM48S8030C KM48S8030C 10/AP

    KM48S8030C

    Abstract: KM48S803 PC133 1998
    Text: KM48S8030C Preliminary PC133 CMOS SDRAM Revision History Revision 0.0 Oct., 1998 • PC133 first published. REV. 0 Oct. '98 Preliminary PC133 CMOS SDRAM KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The KM48S8030C is 67,108,864 bits synchronous high data


    Original     		PDF KM48S8030C PC133 KM48S8030C A10/AP KM48S803 PC133 1998

    TC5118160

    Abstract: msm-561 TMS444000 msm561 M5M418165 M5M418160 tms44c256 TC5117405 HY514264 HY514260
    Text: New Page 1 DRAM 1Meg 1Mx1 256Kx4 FPM FPM Fujitsu MB81C100 MB81C4256 Goldstar GM71C100 GM71C4256 Hitachi HM511000 HM514256 Hyundai HY531000 HY534256 Micron MT4C1024 MT4C4256 Mitsubishi M5M41000 M5M44256 Nec UPD421000 UPD424256 Oki MSM511000 MSM514256 Samsung alt KM41C1000 KM44C256


    Original     		PDF 256Kx4 MB81C100 MB81C4256 GM71C100 GM71C4256 HM511000 HM514256 HY531000 HY534256 MT4C1024 TC5118160 msm-561 TMS444000 msm561 M5M418165 M5M418160 tms44c256 TC5117405 HY514264 HY514260

    Untitled

    Abstract: No abstract text available
    Text: KMM374S823CTS PC100 Unbuffered DIMM Revision History Revision 0.1 Mar. 24, 1999 - Changed "Detail C" in PCB Dimension. - Changed decoupling capacitance from two 0.1uF to one 0.1uF and one 0.33 uF. Rev.0.1 Mar 1999 KMM374S823CTS PC100 Unbuffered DIMM KMM374S823CTS SDRAM DIMM


    Original     		PDF KMM374S823CTS PC100 KMM374S823CTS 8Mx72 400mil 168-pin

    Untitled

    Abstract: No abstract text available
    Text: KMM374S1623BT PC100 SDRAM MODULE Revision History Revision .0 February 1998 - Input leakage Currents (Inputs / DQ) of Component level are changed. I IL(Inputs) : ± 5uA to ± 1uA, I IL(DQ) : ± 5uA to ± 1.5uA. - Cin to be measured at V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV.


    Original     		PDF KMM374S1623BT PC100 118DIA 000DIA 150Max 81Max) 010Max KM48S8030BT

    Untitled

    Abstract: No abstract text available
    Text: SDRAM MODULE Preliminary KMM377S823BT1 Revision History Revision 3 May 1998 - CLK Input Cap. is added by PLL Input Cap. (24pF) Revision 4 (July 1998) - "REGE" description is changed. Revision 5 (Aug. 1998) - Package Dimension changed. REV. 5 Aug. 1998 Preliminary


    Original     		PDF KMM377S823BT1 KMM377S823BT1 8Mx72 400mil 18-bits 100MHz 100MHz

    KM48S8030

    Abstract: KMM350S823BT1-GL
    Text: SDRAM MODULE Preliminary KMM350S823BT1 Revision History Revision 3 July 1998 - "REGE" description is changed. Revision 4 ( Aug. 1998) - Package Dimension changed REV. 4 Aug. 1998 Preliminary KMM350S823BT1 SDRAM MODULE KMM350S823BT1 SDRAM DIMM (Intel 1.0 ver. Base)


    Original     		PDF KMM350S823BT1 KMM350S823BT1 8Mx72 400mil 18-bits 168p1h 100MHz KM48S8030 KMM350S823BT1-GL

    KM48S8030BT-G10

    Abstract: KM48S8030BT KM48S8030BT-G
    Text: KMM374S823BTL PC66 SDRAM MODULE Revision History Revision .3 Mar. 1998 •Some Parameter values & Characteristics of comp. level are changed as below : - Input leakage currents (Inputs) : ±5uA to ±1uA. - Input leakage currents (I/O) : ±5uA to ±1.5uA.


    Original     		PDF KMM374S823BTL 200mV. 66MHz KM48S8030BT-G10 KM48S8030BT KM48S8030BT-G

    KMM375S1723T-G0

    Abstract: KMM375S1723T-G8 KMM375S1723T-GH KMM375S1723T-GL
    Text: Preliminary KMM375S1723T SDRAM MODULE KMM375S1723T SDRAM DIMM 16Mx72 SDRAM DIMM with PLL & Register based on 16Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM375S1723T is a 16M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM375S1723T consists of nine CMOS 16Mx8 bit


    Original     		PDF KMM375S1723T KMM375S1723T 16Mx72 16Mx8, 16Mx8 400mil 18-bits 24-pin KMM375S1723T-G0 KMM375S1723T-G8 KMM375S1723T-GH KMM375S1723T-GL

    KMM374S823DTS-GA

    Abstract: No abstract text available
    Text: KMM374S823DTS PC133 Unbuffered DIMM Revision History Revision 0.0 May, 1999 • PC133 first published. REV. 0 May 1999 KMM374S823DTS PC133 Unbuffered DIMM KMM374S823DTS SDRAM DIMM 8Mx72 SDRAM DIMM with ECC based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD


    Original     		PDF KMM374S823DTS PC133 KMM374S823DTS 8Mx72 400mil KMM374S823DTS-GA

    Untitled

    Abstract: No abstract text available
    Text: Preliminary SDRAM R evision H istory R evision 1 M ay 1998 - ICC2 N va lu e (10m A) is cha ng ed to 12m A. Revision .2 (June 1998) - tSH (-10 binning) is revised. REV. 2 June '98 ELECTRONICS Preliminary


    OCR Scan     		PDF KM48S8030C_ KM48S8030C KM48S8030C 10/AP

    KM48S8030BT

    Abstract: No abstract text available
    Text: KM48S8030B CMOS SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The KM48S8030B is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG'S high performance CMOS technol­


    OCR Scan     		PDF KM48S8030B KM48S8030B KM48S8030BT

    Untitled

    Abstract: No abstract text available
    Text: KM48S8030B CMOS SDRAM Revision History Revision .3 N ovem ber 1997 - tRDL has changed 10ns to 12ns. - Binning -10 does not m eet PC100 characteristics . So AC param eter/C haracteristics have changed to 64M 2nd values. Revision .4 (February 1998) - Input leakage C urrents (Inputs / DQ) are changed.


    OCR Scan     		PDF KM48S8030B PC100 10/AP

    KM48S8030AT

    Abstract: M14e
    Text: KM48S8030A CMOS SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION . • •• rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG'S high performance CMOS technol­ . . - JEDEC standard 3.3V power supply


    OCR Scan     		PDF KM48S8030A KM48S8030A KM48S8030AT M14e

    Untitled

    Abstract: No abstract text available
    Text: Preliminary CMOS SDRAM KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION • • • • The KM48S8030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG'S high performance CMOS technol­


    OCR Scan     		PDF KM48S8030C KM48S8030C 10/AP

    KM48S8030AT

    Abstract: GD33 8030A
    Text: KM48S8030AT SDRAM ELECTR ONICS 2M x 8Bit x 4 Bank Synchronous DRAM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V Power Supply. • LVTTL/SSTL_3 Class II compatible with multiplexed address. • 4 banks operation. • MRS cycle with address key programs.


    OCR Scan     		PDF KM48S8030AT KM48S8030A/KM48S8031A KM48S8030AT) D0334S3 KM48S8030AT GD33 8030A

    Untitled

    Abstract: No abstract text available
    Text: KMM466S823BT2 144pin SDRAM SODIMM Revision History R evision .2 M arch 1998 Som e Param eter values & C hracteristics of comp, level are changed as below : - Input leakage Currents (Inputs) : ± 5uA to ± 1 uA. Input leakage Currents (I/O) : ± 5uA to ± 1,5uA.


    OCR Scan     		PDF KMM466S823BT2 144pin KM48S8030BT

    Untitled

    Abstract: No abstract text available
    Text: PC66 SDRAM MODULE KMM374S1623BTL Revision History Revision .3 March 1998 Som e Param eter value s & C haracteristics of com p, level are changed as below : - Input leakage currents (Inputs) : ± 5 u A to ±1uA. - Input leakage currents (I/O) : ± 5 u A to ± 1 ,5uA.


    OCR Scan     		PDF KMM374S1623BTL KM48S8030BT

    Untitled

    Abstract: No abstract text available
    Text: KMM374S1 623BT PC100 SDR AM M O D U L E Re vis ion Hist ory Revision .0 February 1998 -Input leakage Currents (Inputs / DQ) of Component level are changed. llL(lnputs) : ± 5uA to ± 1uA, llL(DQ) : ± 5uA to ± 1.5uA. -C in to be measured at V DD = 3.3V, T a = 23°C, f = 1MHz, V


    OCR Scan     		PDF KMM374S1 623BT PC100 KMM374S1 150Max KM48S8030BT

    Untitled

    Abstract: No abstract text available
    Text: KMM366S823BTL PC66 SDRAM MODULE KMM366S823BTL SDRAM DIMM 8Mx64 SDRAM DIMM based on 8Mx8,4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM366S823BTL is a 8M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung


    OCR Scan     		PDF KMM366S823BTL KMM366S823BTL 8Mx64 400mil 168-pin KMM366S8238TL 000DIA±