Untitled
Abstract: No abstract text available
Text: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - CC/HDLC ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter
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XRT79L71
XRT79L71
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IDT3051
Abstract: hdlc 17X17 GR-253 GR-499-CORE XRT79L71 XRT79L71IB t59b
Text: PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMER/LIU COMBO - HARDWARE OCTOBER 2010 GENERAL DESCRIPTION REV. P2.0.0 • Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation The XRT79L71 is a single channel, integrated DS3/
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XRT79L71
XRT79L71
IDT3051
hdlc
17X17
GR-253
GR-499-CORE
XRT79L71IB
t59b
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C4106
Abstract: AD27 I960 XRT94L33 XRT94L33IB
Text: XRT94L33 333-C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T A T M P P P H A R W A R E M A N U A L CH HA AN NN NE EL LD DS S333///E E333///S ST TS S-111 T TO OS ST TS S-333///S ST TM M-111 M MA AP PP PE ER RS SO ON NE ET TA AT TM
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XRT94L33
XRT94L33
C4106
AD27
I960
XRT94L33IB
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AD27
Abstract: I960 XRT94L31 XRT94L31IB AF6A 3 pin
Text: XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC MARCH 2007 GENERAL DESCRIPTION The XRT94L31 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/demapping functions from either the STS-3 or STM-1 data stream. The XRT94L31 interfaces directly to the
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XRT94L31
XRT94L31
AD27
I960
XRT94L31IB
AF6A 3 pin
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CHN G4 136
Abstract: chn7 SA8 357 TR54016 XRT83L38 XRT84L38 XRT84L38IB 7174B 8ch LOW SATURATION DRIVER C1-168
Text: XRT84L38 OCTAL T1/E1/J1 FRAMER SEPTEMBER 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error
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XRT84L38
XRT84L38
CHN G4 136
chn7
SA8 357
TR54016
XRT83L38
XRT84L38IB
7174B
8ch LOW SATURATION DRIVER
C1-168
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dmo 265 r
Abstract: dmo 365 r MPC860 jtag AC16 GR-499-CORE I960 MPC860 XRT73L03 XRT74L73 XRT74L73IB
Text: XRT74L73 PRELIMINARY 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER OCTOBER 2003 REV. P1.0.1 GENERAL DESCRIPTION The XRT74L73 3 Channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller is designed to support ATM direct mapping and
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XRT74L73
XRT74L73
dmo 265 r
dmo 365 r
MPC860 jtag
AC16
GR-499-CORE
I960
MPC860
XRT73L03
XRT74L73IB
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MCP860
Abstract: 95L53
Text: XRT95L524 Multi-Port Ethernet MAC Aggregator Data Sheet Revision 0.5 September 20, 2007 EXAR Corporation 48720 Kato Road Fremont, CA. 94538 510 668-7000 www.exar.com Preliminary Version Copyright 2007 EXAR Corporation EXAR Corporation reserves the right to make changes to the products contained in this publication in order
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XRT95L524
org/getieee802/802
//ieee802
1D-1998
org/rfc/rfc2698
-drafts/draft-ietf-pwe3-ethernet-encap-05
drafts/draft-ietf-pwe3control-protocol-04
et-drafts/draft-ietf-pwe3-fcsretention-00
MCP860
95L53
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Untitled
Abstract: No abstract text available
Text: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE DESCRIPTION OCTOBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter
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XRT79L71
XRT79L71
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DMO 565 R
Abstract: No abstract text available
Text: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - ATM ARCHITECTURAL DESCRIPTION NOVEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter
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XRT79L71
XRT79L71
DMO 565 R
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N30 transformer core
Abstract: transformer e19 GR-253-CORE XRT86SH328 XRT86SH328IB
Text: Datasheet, P1.0.1, September 2005 INTEGRATED 28-CHANNEL T1/E1 LIU/FRAMER, VT/TU MAPPER AND M13 MULTIPLEXER XRT86SH328 Network & Transmission Products XRT86SH328 Datasheet GENERAL DESCRIPTION 1 GENERAL DESCRIPTION • Supports 21 E1 mapped as Asynchronous VT2 into an
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28-CHANNEL
XRT86SH328
TU-12
TU-12/VC-11/
TUG-2/TU-11
TU-12
5/TU-11
VT-2/TU-12
N30 transformer core
transformer e19
GR-253-CORE
XRT86SH328
XRT86SH328IB
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CHN G4 124
Abstract: CHN G4 329
Text: áç XRT84L38 PRELIMINARY OCTAL T1/E1/J1 FRAMER JULY 2003 REV. P1.0.4 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications.
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XRT84L38
XRT84L38
CHN G4 124
CHN G4 329
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8051 Read Write for 80c188
Abstract: 68HC11 80C188 I960 TS16 XRT84V24 XRT84V24IV-208 E1 frame FSRC
Text: áç XRT84V24 PRELIMINARY QUAD E1 FRAMER IC JUNE 2001 REV. P1.0.4 GENERAL DESCRIPTION • Contains two 96 byte Transmit HDLC Buffers and two 96 byte Receive HDLC buffers for each channel The XRT84V24 Quad E1 Framer contains four independent E1 Framer blocks. Each E1 Framer block
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XRT84V24
XRT84V24
8051 Read Write for 80c188
68HC11
80C188
I960
TS16
XRT84V24IV-208
E1 frame
FSRC
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IC E3 F6
Abstract: GR-253 XRT94L43
Text: XRT94L43 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER NOVEMBER 2006 GENERAL DESCRIPTION The XRT94L43 is an SDH to PDH physical layer processor with integrated SONET OC-12 and 12 DS3/E3 framing controller. The XRT94L43 contains an integral SONET framer which provides framing
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XRT94L43
OC-12
12XDS3/E3
XRT94L43
STS-12/STM-4
IC E3 F6
GR-253
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Digital Alarm Clock using 8051
Abstract: tle 4246 g osc 16.000 3.3v 32.768mhz ic 0xn8 ac/ac voltage controller octal tri state buffer ic transistor substitution chart XRT83L38 XRT84L38
Text: áç XRT84L38 PRELIMINARY OCTAL T1/E1/J1 FRAMER DECEMBER 2001 REV. P1.0.1 GENERAL DESCRIPTION Link Terminal Equipment direct access to the outbound T1/E1/J1 frames Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the
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XRT84L38
XRT84L38
Digital Alarm Clock using 8051
tle 4246 g
osc 16.000 3.3v
32.768mhz ic
0xn8
ac/ac voltage controller
octal tri state buffer ic
transistor substitution chart
XRT83L38
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Digital Alarm Clock using 8051
Abstract: chn 448 chn 706 CHN 632 CHN 703 RAM 2112 256 word 32.768mhz pin hole thru chn 608 microcontroller 8051 application of alarm clock octal tri state buffer ic
Text: áç XRT84L38 OCTAL T1/E1/J1 FRAMER FEBRUARY 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications.
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XRT84L38
XRT84L38
Digital Alarm Clock using 8051
chn 448
chn 706
CHN 632
CHN 703
RAM 2112 256 word
32.768mhz pin hole thru
chn 608
microcontroller 8051 application of alarm clock
octal tri state buffer ic
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dmo 465
Abstract: No abstract text available
Text: xr PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - PPP ARCHITECTURAL DESCRIPTION DECEMBER 2005 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter
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XRT79L71
XRT79L71
dmo 465
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block diagram for ic 7404 input id
Abstract: dmo 365 r 17X17 GR-253 GR-499-CORE MPC860 XRT79L71 XRT79L71IB C5339 equalizer ic 5218
Text: PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE OCTOBER 2010 GENERAL DESCRIPTION The XRT79L71 is a single channel, integrated DS3/ E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support Frame processing. For Clear-Channel Framer applications, this
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XRT79L71
XRT79L71
block diagram for ic 7404 input id
dmo 365 r
17X17
GR-253
GR-499-CORE
MPC860
XRT79L71IB
C5339
equalizer ic 5218
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ic 339
Abstract: rele nais dmo 465 XRT74L74 XRT74L74IB MIPS 32-bit bus architecture F25 marking DMO 465 R
Text: XRT74L74 PRELIMINARY 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER OCTOBER 2003 REV. P1.1.1 GENERAL DESCRIPTION The XRT74L74 4 Channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller is designed to support ATM direct mapping and
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XRT74L74
XRT74L74
ic 339
rele nais
dmo 465
XRT74L74IB
MIPS 32-bit bus architecture
F25 marking
DMO 465 R
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XRT79L71IB
Abstract: 17X17 GR-253 GR-499-CORE XRT79L71
Text: XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE JUNE 2007 GENERAL DESCRIPTION The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter Attenuator that is designed to support ATM direct
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XRT79L71
XRT79L71
XRT79L71IB
17X17
GR-253
GR-499-CORE
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Untitled
Abstract: No abstract text available
Text: XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC OCTOBER 2006 GENERAL DESCRIPTION The XRT94L31 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/demapping functions from either the STS-3 or STM-1 data stream. The XRT94L31 interfaces directly to the
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XRT94L31
XRT94L31
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MPC860 jtag
Abstract: IBM 236 telecom bus
Text: XRT94L43 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER NOVEMBER 2006 GENERAL DESCRIPTION The XRT94L43 is an SDH to PDH physical layer processor with integrated SONET OC-12 and 12 DS3/E3 framing controller. The XRT94L43 contains an integral SONET framer which provides framing
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XRT94L43
OC-12
12XDS3/E3
XRT94L43
STS-12/STM-4
inter/STS-12
516-ball
MPC860 jtag
IBM 236
telecom bus
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prbs parity checker and generator
Abstract: RGPI5 4-bit even parity checker circuit diagram BY339 relay cross reference AC03 nec SDH 209 XRT95L34 XRT95L34IV b20 p03
Text: áç PRELIMINARY XRT95L34 OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S APRIL 2002 GENERAL DESCRIPTION The XRT95L34 is an OC-12/STM-4, Quad OC-3/ STM-1 POS/ATM Framer with integrated CDR’s. ATM direct mapping and cell delineation are supported, so
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XRT95L34
OC-12/STM-4,
XRT95L34
584-pin
prbs parity checker and generator
RGPI5
4-bit even parity checker circuit diagram
BY339
relay cross reference
AC03 nec
SDH 209
XRT95L34IV
b20 p03
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dmo 365 r
Abstract: RUR 117-5 ELLS 110 PC403 XRT79L71 XRT79L71IB 17X17 GR-253 GR-499-CORE E1 HDB3
Text: áç PRELIMINARY XRT79L71 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC JUNE 2003 REV. P1.0.3 GENERAL DESCRIPTION • JTAG Interface The XRT79L71 is a single channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller and Line Interface Unit with Jitter
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XRT79L71
XRT79L71
dmo 365 r
RUR 117-5
ELLS 110
PC403
XRT79L71IB
17X17
GR-253
GR-499-CORE
E1 HDB3
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