Asus MONITOR MOTHERBOARD CIRCUIT MANUAL
Abstract: T2D 83 diode gp026 st GP025 82430TX 82371EB Asus PC MOTHERBOARD CIRCUIT schematic diode T75A Asus PC MOTHERBOARD CIRCUIT MANUAL 8272A floppy disk controller block diagram
Text: PRELIMINARY DRAFT Intel Extended Temperature 82371EB PCI-TO-ISA/IDE Xcelerator PIIX4E Datasheet Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation Supported Kits for both Pentium and
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82371EB
32-bit
82430TX
82440LX
82371EB
CLK48
Asus MONITOR MOTHERBOARD CIRCUIT MANUAL
T2D 83 diode
gp026 st
GP025
Asus PC MOTHERBOARD CIRCUIT schematic
diode T75A
Asus PC MOTHERBOARD CIRCUIT MANUAL
8272A floppy disk controller block diagram
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m12g
Abstract: 3327-1 dmo 365 r dmo 265 r I148
Text: áç XRT72L13 PRELIMINARY M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC SEPTEMBER 2000 REV. P1.0.5 GENERAL DESCRIPTION The XRT72L13 is a fully integrated, low power, Multiplexer/Framer IC which performs Multiplexing/Demutiplexing of 28 DS1or 21 E1 signals into/from a
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XRT72L13
XRT72L13
m12g
3327-1
dmo 365 r
dmo 265 r
I148
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r4363
Abstract: CP Clare RELAY dmo 465 IC 404
Text: áç XRT72L53 PRELIMINARY THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.6 GENERAL DESCRIPTION The XRT72L53, 3 Channel DS3/E3 Framer IC is designed to accept User Data from the Terminal Equipment and insert this data into the Payload bit-fields
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XRT72L53
XRT72L53,
XRT72L53
DS3-M13,
r4363
CP Clare RELAY
dmo 465
IC 404
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T3D 34 diode
Abstract: 82440LX Diode T3D 57 t57b T27b t59b T31C Transistor t59c ISA BUS spec t119
Text: E DATASHEET ADDENDUM 82371AB PIIX4 PCI ISA IDE Xcelerator Timing Specifications September 1997 Order Number: 290548-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions
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82371AB
T3D 34 diode
82440LX
Diode T3D 57
t57b
T27b
t59b
T31C Transistor
t59c
ISA BUS spec
t119
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IDT3051
Abstract: hdlc 17X17 GR-253 GR-499-CORE XRT79L71 XRT79L71IB t59b
Text: PRELIMINARY XRT79L71 1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMER/LIU COMBO - HARDWARE OCTOBER 2010 GENERAL DESCRIPTION REV. P2.0.0 • Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation The XRT79L71 is a single channel, integrated DS3/
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XRT79L71
XRT79L71
IDT3051
hdlc
17X17
GR-253
GR-499-CORE
XRT79L71IB
t59b
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ATM timing diagram
Abstract: addressing mode motorola 68000 hdlc LAN switch with HDLC GR-253 GR-499-CORE PC403 XRT79L74 XRT79L74IB
Text: PRELIMINARY XRT79L74 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC MARCH 2004 HARDWARE MANUAL The XRT79L74 is a four channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controllers and Line Interface Units with Jitter Attenuators that are designed to support ATM direct
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XRT79L74
XRT79L74
ATM timing diagram
addressing mode motorola 68000
hdlc
LAN switch with HDLC
GR-253
GR-499-CORE
PC403
XRT79L74IB
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B628
Abstract: datasheet relay NAIS 5v 5 pin iC 458 XRT72L58 "Encoder IC" NAIS 210 RELAY octal tri state buffer ic DS3-M13 XRT72L58IB TTB-11
Text: áç XRT72L58 PRELIMINARY EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The XRT72L58 Octal DS3/E3 Framer is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bit-fields within an
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XRT72L58
XRT72L58
DS3-M13,
B628
datasheet relay NAIS 5v 5 pin
iC 458
"Encoder IC"
NAIS 210 RELAY
octal tri state buffer ic
DS3-M13
XRT72L58IB
TTB-11
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hdlc
Abstract: IBM POS GR-253 GR-499-CORE PC403 XRT79L72 XRT79L72IB
Text: xr PRELIMINARY XRT79L72 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC FEBRUARY 2005 HARDWARE MANUAL The XRT79L72 is a two channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controllers and Line Interface Units with Jitter Attenuators that are designed to support ATM direct
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XRT79L72
XRT79L72
hdlc
IBM POS
GR-253
GR-499-CORE
PC403
XRT79L72IB
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dmo 365 r
Abstract: datasheet relay NAIS 5v 5 pin NAIS Relay 5v bi directional dc motor speed controller NAIS 210 NAIS 210 RELAY 5v relay nais 5 pin data sheet DS3-M13 sha t90 T79 code marking
Text: áç XRT72L53 PRELIMINARY THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER FEBRUARY 2001 REV. P1.1.7 GENERAL DESCRIPTION The XRT72L53, 3 Channel DS3/E3 Framer IC is designed to accept User Data from the Terminal Equipment and insert this data into the Payload bit-fields
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XRT72L53
XRT72L53,
XRT72L53
DS3-M13,
dmo 365 r
datasheet relay NAIS 5v 5 pin
NAIS Relay 5v
bi directional dc motor speed controller
NAIS 210
NAIS 210 RELAY
5v relay nais 5 pin data sheet
DS3-M13
sha t90
T79 code marking
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dmo 365 rn
Abstract: DMO36 dmo 365 r IC TX 434 HDB3 AMI ENCODER DECODER t90 series DS3-M13 XRT7250 XRT7250IQ difference between 8051 and 8052 microcontroller
Text: áç XRT7250 PRELIMINARY DS3/E3 FRAMER IC MARCH 2000 REV. P1.0.5 GENERAL DESCRIPTION The XRT7250 DS3/E3 Framer IC is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bit-fields within an “outbound” DS3/E3 Data Stream. Further, the Framer
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XRT7250
XRT7250
DS3-M13,
dmo 365 rn
DMO36
dmo 365 r
IC TX 434
HDB3 AMI ENCODER DECODER
t90 series
DS3-M13
XRT7250IQ
difference between 8051 and 8052 microcontroller
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T55B
Abstract: T71A t19c t17c t61b t58b t57b T27b t65a T3D 62
Text: 82371AB PCI ISA IDE Xcelerator PIIX4 23.0 Clock, Reset, ISA Bus, X-Bus, and Host Timing Diagrams Figure 41. Clock Timing Period High Time PCICLK, SYSCLK, OSC 2.0V 0.8V Low Time Fall Time Rise Time Figure 42. Reset Inactive Timing SUS_STAT[1:2]# t2f PCIRST#, RSTDRV
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82371AB
IRQ13
IRQ12/M,
T55B
T71A
t19c
t17c
t61b
t58b
t57b
T27b
t65a
T3D 62
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dmo 465
Abstract: iC 458 datasheet relay NAIS 5v 5 pin M25-A dmo 365 dmo 365 r NAIS 210 RELAY NAIS Relay 5v DS3-M13 XRT72L56
Text: áç XRT72L56 PRELIMINARY SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The Microprocessor Interface is used to configure the Framer in different operating modes and monitor the performance of the Framer. The XRT72L56, 6 Channel DS3/E3 Framer is designed to accept “User Data” from the Terminal
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XRT72L56
XRT72L56,
XRT72L56
dmo 465
iC 458
datasheet relay NAIS 5v 5 pin
M25-A
dmo 365
dmo 365 r
NAIS 210 RELAY
NAIS Relay 5v
DS3-M13
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dmo 365 r
Abstract: dmo 365 dmo 465 datasheet relay NAIS 5v 5 pin marx and generator NAIS 210 RELAY NAIS Relay 5v DS3-M13 XRT72L52 XRT72L52IQ
Text: XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER OCTOBER 2006 REV. 1.0.3 GENERAL DESCRIPTION The XRT72L52, Two Channel DS3/E3 Framer IC is designed to accept user data from the Terminal Equipment and insert this data into the payload bitfields within an outbound DS3/E3 Data Stream.
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XRT72L52
XRT72L52,
XRT72L52
DS3-M13,
dmo 365 r
dmo 365
dmo 465
datasheet relay NAIS 5v 5 pin
marx and generator
NAIS 210 RELAY
NAIS Relay 5v
DS3-M13
XRT72L52IQ
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NAIS 210 RELAY
Abstract: ic 393 k 4213 0X13 DS3-M13 XRT72L52
Text: áç XRT72L52 PRELIMINARY TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The XRT72L52, 2 Channel DS3/E3 Framer IC is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bitfields within an “outbound” DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an “inbound” DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the “User Data”.
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XRT72L52
XRT72L52,
XRT72L52
DS3-M13,
NAIS 210 RELAY
ic 393
k 4213
0X13
DS3-M13
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY XRT79L72 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC MARCH 2004 HARDWARE MANUAL The XRT79L72 is a two channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controllers and Line Interface Units with Jitter Attenuators that are designed to support ATM direct
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XRT79L72
XRT79L72
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Untitled
Abstract: No abstract text available
Text: áç XRT72L50 PRELIMINARY SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.3 GENERAL DESCRIPTION The XRT72L50, single Channel DS3/E3 Framer IC is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bitfields within an “outbound” DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an “inbound” DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the “User Data”.
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XRT72L50
XRT72L50,
XRT72L50
DS3-M13,
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Rx1302
Abstract: r4363 dmo 265
Text: áç XRT72L50 PRELIMINARY SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The XRT72L50, single Channel DS3/E3 Framer IC is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bitfields within an “outbound” DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an “inbound” DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the “User Data”.
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XRT72L50
XRT72L50,
XRT72L50
DS3-M13,
Rx1302
r4363
dmo 265
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PDF
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4558AM
Abstract: dmo 465
Text: XRT72L52 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER OCTOBER 2006 REV. 1.0.3 GENERAL DESCRIPTION The XRT72L52, Two Channel DS3/E3 Framer IC is designed to accept user data from the Terminal Equipment and insert this data into the payload bitfields within an outbound DS3/E3 Data Stream.
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XRT72L52
XRT72L52,
XRT72L52
DS3-M13,
XRT72L52IQ-F
PQFP160
31-Jul-09
4558AM
dmo 465
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82378ib
Abstract: No abstract text available
Text: A P M Ä M ! DM iP© I^[ìfflA'irD@ N] in te i 82378IB SYSTEM I/O SIO Provides the Bridge Between the PCI Bus and ISA Bus Arbitration for PCI Devices — Four PCI Masters are Supported — Fixed, Rotating, or a Combination of the Two 100% PCI and ISA Compatible
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82378IB
IOCS16#
MEMCS16#
82378ib
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oms 450
Abstract: PT2622 2N1841 BLY81 2SC115 BLY74 M06G A515 B3570 B3571
Text: SY M B O L S & C O D ES E X P L A IN E D 7. "N ” Channel - SILICON FIELD EFFECT TRANSISTORS 8. GERMANIUM P N P 1 9 GERMANIUM N PN 110. SILICON PNP 11. SILICON NPN High Power Transistors k I B L IN E No. H H TYPE No. I I M IN . ID E R A T E J to C M AX Pc
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NPN110.
350kA
2N2342t
550kA
2N2343
BLY81
25OuA0
400nS
BLY87
oms 450
PT2622
2N1841
2SC115
BLY74
M06G
A515
B3570
B3571
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dma controller chip
Abstract: No abstract text available
Text: in tj, 82374EB EISA SYSTEM COMPONENT ESC • Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Wait State Cycles — Supports Byte Assembly/ Disassembly for 8-, 16- and 32-Bit
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82374EB
32-Bit
82C37A
dma controller chip
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78m5
Abstract: mt59 PT2622
Text: SY M B O L S & C O D ES E X P L A IN E D 7. "N ” Channel - SILICON FIELD EFFECT TRANSISTORS 8. GERMANIUM P N P 1 9 GERMANIUM N PN 110. SILICON PNP 11. SILICON NPN High Power Transistors LINE No. k I B H H TYPE No. ABSOiLOTE MAX. RATIINGS Ä 2 5 C I I MIN. MAX Pc T6TT
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82353
Abstract: intel 82358 82359 82353 intel intel 82353 82358DT
Text: 82353 ADVANCED DATA PATH • Dual Port Architecture Allows Host to Access Memory without Incurring EISA Arbitration ■ Provides Optimal i486 Burst Performance ■ High Performance, Flexible Memory Support: — Designed as a 16-Bit Slice which Interfaces 16, 32, or 64-Bit Memory
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16-Bit
64-Bit
82353s
128-Bit
32-Bit
164-Pin
t109A
t120A
t120B
82353
intel 82358
82359
82353 intel
intel 82353
82358DT
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82374EB/82374SB
Abstract: No abstract text available
Text: Ä I W Ä 1 OMIF ISBM!rD@M in tei 82374EB EISA SYSTEM COMPONENT ESC Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Wait State Cycles — Supports Byte Assembly/
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82374EB
32-Bit
MASTER16#
82374EB/82374SB
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