CMS3216LAF
Abstract: CMS3216LAG CMS3216LAH
Text: CMS3216LAx-75xx 32M 2Mx16 Low Power SDRAM Revision 0.2 January, 2007 Rev0.2, Jan. 2007 CMS3216LAx-75xx Document Title 32M(2Mx16) Low Power SDRAM Revision History Revision No. History Draft date Remark 0.0 Initial Draft Mar.3rd, 2005 Preliminary 0.1 Add H(Pb-Free & Halogen Free) descriptions
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CMS3216LAx-75xx
2Mx16)
CMS3216LAF
CMS3216LAG
CMS3216LAH
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ba1s
Abstract: No abstract text available
Text: IS43LR32400E Advanced Information 1M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43LR32400E is 134,217,728 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The address lines are multiplexed with the Data
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IS43LR32400E
32Bits
IS43LR32400E
Figure38
90Ball
-25oC
4Mx32
IS43LR32400E-6BLE
ba1s
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IS43LR16640A
Abstract: IS43LR16640A-5BLI IS43LR16640A-6BLI IS46LR16640A-5BLA1 IS43LR16640A-6BL
Text: IS43/46LR16640A Advanced Information 16M x 16Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR16640A is 1,073,741,824 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 16,777,216 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
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IS43/46LR16640A
16Bits
IS43/46LR16640A
16-bit
-40oC
64Mx16
IS43LR16640A-5BLI
IS43LR16640A-6BLI
60-ball
IS43LR16640A
IS46LR16640A-5BLA1
IS43LR16640A-6BL
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bt 2323
Abstract: TX-2G
Text: AWL9966 802.11a/b/g/n WLAN/Bluetooth FEIC PRELIMINARY DATA SHEET - Rev 1.2 FEATURES • 3% Dynamic EVM @ POUT = +17 dBm with IEEE 802.11a 64 QAM OFDM at 54 Mbps • 3% Dynamic EVM @ POUT = +20 dBm with IEEE 802.11g 64 QAM OFDM at 54 Mbps • -30 dBc 1st Sidelobe / -50 dBc 2nd Sidelobe
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11a/b/g/n
AWL9966
bt 2323
TX-2G
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46LR32640A
Abstract: Mobile DDR SDRAM
Text: IS43/46LR32640A 16M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32640A is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 33,554,432 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
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IS43/46LR32640A
32Bits
IS43/46LR32640A
32-bit
IS43LR32640A-6BLI
90-ball
-40oC
64Mx32
IS46LR32640A-5BLA1
46LR32640A
Mobile DDR SDRAM
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CMS3216LAF
Abstract: CMS3216LAG CMS3216LAH
Text: CMS3216LAx-75Ex 32M 2Mx16 Low Power SDRAM Revision 0.1 November, 2005 Rev0.1, Nov. 2005 CMS3216LAx-75Ex Document Title 32M(2Mx16) Low Power SDRAM Revision History Revision No. History Draft date Remark 0.0 Initial Draft Mar.3rd, 2005 Preliminary 0.1 Add H(Pb-Free & Halogen Free) descriptions
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CMS3216LAx-75Ex
2Mx16)
CMS3216LAF
CMS3216LAG
CMS3216LAH
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Untitled
Abstract: No abstract text available
Text: DUAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT IDT82V2082 FEATURES: • • • • • • • - Dual channel T1/E1/J1 long haul/short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays
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IDT82V2082
772KHz
TBR12/13
82V2082
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VOGT n3 503 20 010 50
Abstract: No abstract text available
Text: HFC - S active ISDN Microprocessor ARM7 based Preliminary Data Sheet: July 2002 Copyright 1994 - 2002 Cologne Chip AG All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the information presented may be protected by patent or other rights.
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adp3208
Abstract: APD3208 ADP3208CJCPZ-RL
Text: Preliminary Buck Controller ADP3208C FEATURES GENERAL DESCRIPTION Single-chip solution Fully compatible with the Intel IMVP-6+ specifications Integrated MOSFET drivers Input Voltage Range of 3.3 V to 22 V
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ADP3208C
ADP3208C
adp3208
APD3208
ADP3208CJCPZ-RL
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Untitled
Abstract: No abstract text available
Text: K4Y50164UC K4Y50084UC K4Y50044UC K4Y50024UC XDRTM DRAM TM 512Mbit XDR DRAM C-die Revision 1.0 December 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
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K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
512Mbit
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IST13
Abstract: No abstract text available
Text: CR16MNS5, CR16MFS5, and CR16MPS5 are Obsolete Devices CR16MES5,CR16MES9,CR16MFS5,CR16MFS9, CR16MHS5,CR16MHS9,CR16MNS5,CR16MNS9, CR16MPS5,CR16MUS5,CR16MUS9 6MPS5/CR16MUS5/CR16MUS9 Family of CompactRISC 16-Bit Microcontrollers
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CR16MNS5,
CR16MFS5,
CR16MPS5
CR16MES5
CR16MES9
CR16MFS5
CR16MFS9,
CR16MHS5
CR16MHS9
CR16MNS5
IST13
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D560 transistor
Abstract: nec D560 transistor transistor d560 transistor D1138 KS51850 KS51850 D4 Samsung tv remote control circuit diagram d1138 transistor d560 nec nec D560
Text: 51850 2 KS51850 OVERVIEW KS51850, a 4-bit single-chip CMOS microcontroller, consists of the reliable SMCS-51 CPU core with on-chip ROM and RAM. Eight input pins and 11 output pins provide the flexibility for various I/O requirements. Auto reset circuit generates reset pulse every certain period, and every halt mode termination time. The KS51850
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KS51850
KS51850,
SMCS-51
KS51850
fxx/12
0800h
0900h
0a00h
D560 transistor
nec D560 transistor
transistor d560
transistor D1138
KS51850 D4
Samsung tv remote control circuit diagram
d1138 transistor
d560 nec
nec D560
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46LR16640A
Abstract: Mobile DDR SDRAM
Text: IS43/46LR16640A Advanced Information 16M x 16Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR16640A is 1,073,741,824 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 16,777,216 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
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IS43/46LR16640A
16Bits
IS43/46LR16640A
16-bit
IS43LR16640A-5BL
IS43LR16640A-6BL
60-ball
-40oC
64Mx16
46LR16640A
Mobile DDR SDRAM
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46LR32640A
Abstract: Mobile DDR SDRAM IS43LR32640A-5BLI IS46LR32640A-5BLA1 64Mx32 Mobile DDR SDRAM IS43LR32640A
Text: IS43/46LR32640A Advanced Information 16M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32640A is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 33,554,432 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
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IS43/46LR32640A
32Bits
IS43/46LR32640A
32-bit
IS43LR32640A-5BL
IS43LR32640A-6BL
90-ball
-40oC
64Mx32
46LR32640A
Mobile DDR SDRAM
IS43LR32640A-5BLI
IS46LR32640A-5BLA1
64Mx32 Mobile DDR SDRAM
IS43LR32640A
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446H
Abstract: 451H RDN11 GR-253-CORE GR-499-CORE IDT82P2821 640-Pin
Text: 21 +1 Channel High-Density T1/E1/J1 Line Interface Unit IDT82P2821 Version 3 February 6, 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: 1-800-345-7015 or 408-284-8200• TWX: 910-338-2070 • FAX: 408-284-2775 Printed in U.S.A.
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IDT82P2821
640-pin
BH640)
BHG640)
82P2821
446H
451H
RDN11
GR-253-CORE
GR-499-CORE
IDT82P2821
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BF484
Abstract: IDT82P20516 transformer e19 GR-253-CORE GR-499-CORE 82P20516 chn 347
Text: 16-Channel Short Haul E1 Line Interface Unit IDT82P20516 Version December 17, 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: 1-800-345-7015 or 408-284-8200• TWX: 910-338-2070 • FAX: 408-284-2775 Printed in U.S.A. 2009 Integrated Device Technology, Inc.
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16-Channel
IDT82P20516
484-pin
BF484)
BFG484)
82P20516
82P20516D
BF484
IDT82P20516
transformer e19
GR-253-CORE
GR-499-CORE
82P20516
chn 347
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package detail of IDT82V2081
Abstract: IDT82V2081 TQFP44 TQFP44 package
Text: SINGLE CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT IDT82V2081 FEATURES: • • • • • • • Single channel T1/E1/J1 long haul/short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays
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IDT82V2081
772KHz
TBR12/13
82V2081
package detail of IDT82V2081
IDT82V2081
TQFP44
TQFP44 package
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ILI9325DS_V0.43
Abstract: ILI9325 BIT 3195 G G184 BIT+3195+G ILI9325D
Text: ILI9325 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Datasheet Version: V0.43 Document No.: ILI9325DS_V0.43.pdf ILI TECHNOLOGY CORP. 4F, No. 2, Tech. 5th Rd., Hsinchu Science Park, Taiwan 300, R.O.C. Tel.886-3-5670095; Fax.886-3-5670096
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ILI9325
240RGBx320
ILI9325DS
ILI9325DS_V0.43
ILI9325
BIT 3195 G
G184
BIT+3195+G
ILI9325D
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Untitled
Abstract: No abstract text available
Text: IS43/46LR32200B 512K x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32200B is 67,108,864 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 524,288 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a
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IS43/46LR32200B
32Bits
IS43/46LR32200B
32-bit
IS43LR32200B-6BLI
90-ball
-40oC
2Mx32
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Untitled
Abstract: No abstract text available
Text: I S43LR16200C Advanced Information 1M x 16Bits x 2Banks Mobile DDR SDRAM Description The IS43LR16200C is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2N
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S43LR16200C
16Bits
IS43LR16200C
2Mx16
IS43LR16200C-6BL
60-ball
IS43LR16200C-6BLI
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Untitled
Abstract: No abstract text available
Text: IS43/46LR32800F 2M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32800F is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 2,097,152 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
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IS43/46LR32800F
32Bits
IS43/46LR32800F
32-bit
IS43LR32800F-6BLI
90-ball
-40oC
8Mx32
IS46LR32800F-6BLA1
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c814C
Abstract: F217 EUA4890A EUA4890AHIR1
Text: 芯美电子 EUA4890A 1 Watt Audio Power Amplifier DESCRIPTION FEATURES The EUA4890A is an audio power amplifier designed for portable communication device applications such as mobile phone applications. The EUA4890A is capable of delivering 1.0W of continuous average power to an 8Ω
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EUA4890A
EUA4890A
350mW
DS4890A
c814C
F217
EUA4890AHIR1
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DS5202
Abstract: 3.5mm stereo headphone jack 8ohm 0.5W speakers EUA5202 EUA5202QIT1 15W 50 Ohm Resistors EUA5202QIR0 EUA5202QIR1 Figure37 EUA MARKING CODE Speaker - 0.5W 8Ohm
Text: 芯美电子 EUA5202 2-W Stereo Audio Power Amplifier with Mute DESCRIPTION FEATURES z The EUA5202 is a stereo audio power amplifier that delivering 2W of continuous RMS power per channel into 3-Ω loads. When driving 1W into 8-Ω speakers, the EUA5202 has less than 0.04% THD+N across its
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EUA5202
800mW/ch
TSSOP-24
EUA5202
MO-153
DS5202
3.5mm stereo headphone jack 8ohm 0.5W speakers
EUA5202QIT1
15W 50 Ohm Resistors
EUA5202QIR0
EUA5202QIR1
Figure37
EUA MARKING CODE
Speaker - 0.5W 8Ohm
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AN-532A
Abstract: AN532A MC1648 MC4324/4024 MC1648 equivalent MC74416
Text: INTR O D U C TIO N 1 PHASE-DETECTORS 2 OSCILLATORS - M U L TIV IB R A TO R S 3 M IXERS COUNTERS 5 APPLICATIONS 6 PACKAGING PHASE-LOCKED LOOP DATA BOOK Second Edition August, 1973 MECL, MECL III, MECL 10,000, MTTL, and McMOS are trademarks of Motorola Inc.
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