DS0206
Abstract: TSF0284-L4
Text: Flexibility & Innovation …. DS0206_01 15.05.01 Part Number 284 MHz SAW Filter Pager TSF0284-L4 SPECIFICATION PRODUCT FEATURES : Ø HIGH STABILITY Ø LOW LOSS Ø SMALL SIZE TEMEX S.A.W. CONTACT : PUITS-GODET 8, 2000 NEUCHÂTEL SWITZERLAND TEL. : +41 32 722 18 20
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DS0206
TSF0284-L4
TSF0284-L4
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TTSI016641BL-1
Abstract: STSI-144 TSI-16
Text: Advance Information May 2002 TSI-16 Time-Slot Interchanger Product Description Introduction Features This document is a high-level description for the TSI-16 time-slot interchanger device. The features and functions of the device are listed and explained at a level intended to meet the needs of the system
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TSI-16
DS02-073SWCH
DS02-064BBAC)
TTSI016641BL-1
STSI-144
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GR-253
Abstract: TTRN0110G
Text: Data Sheet March 29, 2002 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Features Applications Supports standard OC-192/STM-64 data rate of 9.95328 Gbits/s up through forward error correction FEC rate of 10.7092 Gbits/s as well as the Ethernet rate of 10.3125 Gbits/s
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TTRN0110G
OC-192/STM-64
transfe0-712-4106)
DS02-062HSPL
DS01-236HSPL)
GR-253
TTRN0110G
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bt34w
Abstract: No abstract text available
Text: Data Sheet January 2002 DSP1629 Digital Signal Processor 1 Features • Optimized for mobile communications applications with a bit manipulation unit for higher coding efficiency. ■ On-chip, programmable, PLL clock synthesizer. ■ 10 ns and 16.7 ns instruction cycle times at 3.0 V,
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DSP1629
DSP1629x16
DSP1629x10
DS02-060AUTO
bt34w
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10Gb CDR
Abstract: D14p N4 Amplifier 1 into 12 demultiplexer circuit diagram pin diagram 14 demultiplexer GR-253 TRCV0110G APD-SBSC-101
Text: Data Sheet March 28, 2002 TRCV0110G 10 Gbits/s Limiting Amplifier Clock Recovery, 1:16 Data Demultiplexer Features • ■ ■ Integrated limiting amplifier with 8 mV sensitivity at 1 x 10–10 bit error rate BER Integrated clock recovery and 1:16 data demultiplexer (deMUX)
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TRCV0110G
OC-192/STM-64
177-ball
s-712-4106)
DS02-061HSPL
DS01-235HSPL)
10Gb CDR
D14p
N4 Amplifier
1 into 12 demultiplexer circuit diagram
pin diagram 14 demultiplexer
GR-253
APD-SBSC-101
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GR-253
Abstract: TRCV0110G TRCV0110G-3-XE APD-SBSC-101
Text: Data Sheet June 7, 2002 TRCV0110G 10 Gbits/s Limiting Amplifier Clock Recovery, 1:16 Data Demultiplexer Features • ■ ■ Integrated limiting amplifier with 7.5 mV sensitivity at 1e-10 bit error rate BER Integrated clock recovery and 1:16 data demultiplexer (deMUX)
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TRCV0110G
1e-10
OC-192/STM-64
177-Ball
DS02-247HSPL
DS02-061HSPL)
GR-253
TRCV0110G-3-XE
APD-SBSC-101
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STSI-144
Abstract: TSI-16 TTSI016641BL-1
Text: Advisory July 2002 TSI-16 Time-Slot Interchanger Introduction TXD Precharge Resistors This document describes technical issues that are known to exist with the device and/or the documentation of the device. TXD[23:00] are not properly equipped with precharge
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TSI-16
DS02-073SWCH
DS02-064BBAC)
STSI-144
TTSI016641BL-1
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LCK4801
Abstract: MPC998 2274a
Text: Preliminary Data Sheet December 2001 LCK4801 Low-Voltage HSTL Differential Clock General Features The LCK4801 is a low-voltage, 3.3 V HSTL differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to
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LCK4801
LCK4801
DS02-069HSI
DS01-234HSI)
MPC998
2274a
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fargo maestro 100 AT Command
Abstract: gsm modem maestro-20 fargo maestro AT Command MAESTRO-100 fargo maestro 100 Fargo WORKING WITH MAESTRO 20 Wavecom AT Command 07.07 gsm modem maestro-100 gsm modem sim 900
Text: GSM20 GSM100T GSM & GPRS MODEM • • • • • • • • • • • • • • GSM and GPRS Voice / Fax / SMS and Data Dual Band 900 / 1800MHz GSM Transmission Full voice call, SMS support Accepts Standard SIM Card Data enabled SIM Cards available
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GSM20
GSM100T
1800MHz
RS232
GSM20:
24Kb/s
12Kb/s
GSM100T:
36Kb/s
fargo maestro 100 AT Command
gsm modem maestro-20
fargo maestro AT Command
MAESTRO-100
fargo maestro 100
Fargo
WORKING WITH MAESTRO 20
Wavecom AT Command 07.07
gsm modem maestro-100
gsm modem sim 900
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0x0041E
Abstract: csg 6522 TSI-16 0x0040c 0X00002
Text: Advance Information May 2002 TSI-16 Time-Slot Interchanger Register Description Introduction Acronyms Used This document defines the address map for the TSI-16 and describes the purpose and operation of each register bit, its dependencies, and its initial
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TSI-16
DS02-074SWCH
DS02-064BBAC)
0x0041E
csg 6522
0x0040c
0X00002
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0x00418
Abstract: rxd40
Text: Advisory July 2002 TSI-16 Time-Slot Interchanger Introduction TXD Precharge Resistors This document describes technical issues that are known to exist with the device and/or the documentation of the device. TXD[23:00] are not properly equipped with precharge
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TSI-16
Action10-12,
DS02-075SWCH
DS02-064BBAC)
0x00418
rxd40
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