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    TTRN0110G Search Results

    TTRN0110G Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    TTRN0110G Agere Systems 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Original PDF
    TTRN0110G Agere Systems TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Original PDF
    TTRN0110G-3-XF-DB Agere Systems SONET Transceiver, 10Gbits/s Clock Synthesizer, 16:1 Data Multiplexed Original PDF

    TTRN0110G Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    GR-253

    Abstract: TTRN0110G
    Text: Data Sheet March 29, 2002 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Features Applications Supports standard OC-192/STM-64 data rate of 9.95328 Gbits/s up through forward error correction FEC rate of 10.7092 Gbits/s as well as the Ethernet rate of 10.3125 Gbits/s


    Original     		PDF TTRN0110G OC-192/STM-64 transfe0-712-4106) DS02-062HSPL DS01-236HSPL) GR-253 TTRN0110G

    TTRN0110G

    Abstract: Interface cross
    Text: Product Brief August 2000 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Features • ■ ■ ■ ■ ■ Fully-integrated 10 GHz clock synthesizer; 16:1 data multiplexer Supports standard OC-192/STM-64 data rate of 9.9532 GHz as well as FEC rate of 10.6642 GHz


    Original     		PDF TTRN0110G OC-192/STM-64 PB00-081HSPL TTRN0110G Interface cross

    TTRN0110G

    Abstract: D10GP 198-pin
    Text: Advance Data Sheet August 2000 TTRN0110G 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Features • Fully-integrated 10 GHz clock synthesizer; 16:1 data multiplexer ■ Supports standard OC-192/STM-64 data rate of 9.9532 GHz as well as FEC rate of 10.6642 GHz


    Original     		PDF TTRN0110G OC-192/STM-64 DS00-346HSPL TTRN0110G D10GP 198-pin

    4-bit GTL to LVTTL transceiver

    Abstract: digital clock using gates ORLI10G TRCV0110G TTRN0110G write operation using ram in fpga
    Text: Product Brief February 2001 ORCA ORLI10G 10 Gbits/s Line Interface FPSC Introduction Lucent Technologies Microelectronics Group has developed a new ORCA Series 4 based FPSC, which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable


    Original     		PDF ORLI10G ORLI10G 16-bit PB01-048NCIP PB01-021NCIP) 4-bit GTL to LVTTL transceiver digital clock using gates TRCV0110G TTRN0110G write operation using ram in fpga

    10Gb CDR

    Abstract: D14p N4 Amplifier 1 into 12 demultiplexer circuit diagram pin diagram 14 demultiplexer GR-253 TRCV0110G APD-SBSC-101
    Text: Data Sheet March 28, 2002 TRCV0110G 10 Gbits/s Limiting Amplifier Clock Recovery, 1:16 Data Demultiplexer Features • ■ ■ Integrated limiting amplifier with 8 mV sensitivity at 1 x 10–10 bit error rate BER Integrated clock recovery and 1:16 data demultiplexer (deMUX)


    Original     		PDF TRCV0110G OC-192/STM-64 177-ball s-712-4106) DS02-061HSPL DS01-235HSPL) 10Gb CDR D14p N4 Amplifier 1 into 12 demultiplexer circuit diagram pin diagram 14 demultiplexer GR-253 APD-SBSC-101

    Internal diagram of ic 7495

    Abstract: optical regenerator OTN SWITCH regenerator in optical 0936A TFEC0410G BA 1153 code of encoder and decoder in rs(255,239) sdh regenerator ic 7495 data sheet
    Text: Product Brief March 2001 TFEC0410G 40 Gbits/s Optical Networking Interface With Strong FEC and Digital Wrapper Features • ■ Versatile IC supports single 2488 Mbits/s 16 bits at 155 Mbits/s , quad 2488 Mbits/s (4 bits at 622 Mbits/s), and single 9952 Mbits/s (16 bits at


    Original     		PDF TFEC0410G STS-48/ STM-16 STS-192/STM-64 STS-48/STM-16 PB01-014SONT PN00-024SONT) Internal diagram of ic 7495 optical regenerator OTN SWITCH regenerator in optical 0936A BA 1153 code of encoder and decoder in rs(255,239) sdh regenerator ic 7495 data sheet

    BL Super p5 sanyo denki

    Abstract: l37a ap13.6 diode BL SUPER P5 Sanyo Denki encoder ORLI10G STM-16 TRCV0110G TTRN0110G TTRN0126
    Text: Data Sheet April, 2002 ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s Line Interface FPSC Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded system-on-chip SoC


    Original     		PDF ORLI10G OIF-SFI4-01 16-bit ORLI10G ORLI10G3BM680-DB ORLI10G2BM680-DB ORLI10G1BM680-DB BL Super p5 sanyo denki l37a ap13.6 diode BL SUPER P5 Sanyo Denki encoder STM-16 TRCV0110G TTRN0110G TTRN0126

    l11D

    Abstract: Sanyo Denki encoder transistor BC 667 ORLI10G TRCV0110G TTRN0110G
    Text: Preliminary Data Sheet July 2001 ORCA ORLI10G Field-Programmable System Chip 10 Gbits/s Transmit and Receive Line Interface Introduction Agere Systems Inc has developed a new ORCA Series 4 based FPSC, which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series


    Original     		PDF ORLI10G 16-bit DS01-269NCIP DS01-229NCIP) l11D Sanyo Denki encoder transistor BC 667 TRCV0110G TTRN0110G

    ORLI10G

    Abstract: STM-16 TRCV0110G TTRN0110G TTRN0126 STM-16 chips
    Text: Data Sheet January 15, 2002 ORCA ORLI10G Quad 2.5 Gbits/s, 10 Gbits/s, and ORLI12G 12.5 Gbits/s Line Interface FPSC Introduction Lattice has developed a new ORCA Series 4-based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4


    Original     		PDF ORLI10G ORLI12G OIF-SFI4-01 16-bit DS02-050NCIP DS01-277NCIP) STM-16 TRCV0110G TTRN0110G TTRN0126 STM-16 chips

    GR-253

    Abstract: TRCV0110G TRCV0110G-3-XE APD-SBSC-101
    Text: Data Sheet June 7, 2002 TRCV0110G 10 Gbits/s Limiting Amplifier Clock Recovery, 1:16 Data Demultiplexer Features • ■ ■ Integrated limiting amplifier with 7.5 mV sensitivity at 1e-10 bit error rate BER Integrated clock recovery and 1:16 data demultiplexer (deMUX)


    Original     		PDF TRCV0110G 1e-10 OC-192/STM-64 177-Ball DS02-247HSPL DS02-061HSPL) GR-253 TRCV0110G-3-XE APD-SBSC-101

    APD-SBSC-101

    Abstract: GR-253 0364a
    Text: Data Sheet September 17, 2002 TRCV0111G2 10 Gbits/s Limiting Amplifier Clock Recovery, 1:16 Data Demultiplexer Features • ■ ■ Integrated limiting amplifier with 7.5 mV sensitivity at 1e-10 bit error rate BER Integrated clock recovery and 1:16 data demultiplexer (deMUX)


    Original     		PDF TRCV0111G2 1e-10 OC-192/STM-64 177-ball DS02-364HSPL APD-SBSC-101 GR-253 0364a

    circuit diagram of 16-1 multiplexer

    Abstract: TTRN0110G TTRN0112G GR-1377-CORE
    Text: Product Brief May 2001 TTRN0112G 12.5 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer Features • ■ ■ ■ ■ ■ ■ Supports OC-192/STM-64 standard and multiple FEC rates and 10GE data rates. Allows for two separate frequency ranges of operation:


    Original     		PDF TTRN0112G OC-192/STM-64 PB01-126HSPL circuit diagram of 16-1 multiplexer TTRN0110G TTRN0112G GR-1377-CORE

    GR-253

    Abstract: TRCV0110G TRCV0110G2 agere 300-pin APDS
    Text: Data Sheet June 17, 2002 TRCV0110G2 10 Gbits/s Limiting Amplifier Clock Recovery, 1:16 Data Demultiplexer Features • Integrated limiting amplifier with 10 mV sensitivity at 1e-10 bit error rate BER ■ Integrated clock recovery and 1:16 data demultiplexer (deMUX)


    Original     		PDF TRCV0110G2 1e-10 OC-192/STM-64 177-Ball DS02-279HSPL GR-253 TRCV0110G agere 300-pin APDS

    design a 4-bit arithmetic logic unit using xilinx

    Abstract: OC192 ORLI10G TRCV0110G TTRN0110G 4-bit GTL to LVTTL transceiver
    Text: Preliminary Product Brief November 2000 ORCA ORLI10G 10 Gbits/s Line Interface FPSC Introduction Lucent Technologies Microelectronics Group has developed a new ORCA Series 4 based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable


    Original     		PDF ORLI10G ORLI10G 16-bit PB01-021NCIP design a 4-bit arithmetic logic unit using xilinx OC192 TRCV0110G TTRN0110G 4-bit GTL to LVTTL transceiver

    TRCV0111G

    Abstract: GR-253
    Text: Data Sheet September 17, 2002 TRCV0111G 10 Gbits/s Limiting Amplifier Clock Recovery, 1:16 Data Demultiplexer Features • ■ ■ Integrated limiting amplifier with 7.5 mV sensitivity at 1e-10 bit error rate BER Integrated clock recovery and 1:16 data demultiplexer (deMUX)


    Original     		PDF TRCV0111G 1e-10 OC-192/STM-64 177-ball DS02-071HSPL GR-253

    BL Super p5 sanyo denki

    Abstract: BL SUPER P5 PLC Communication cables pin diagram Sanyo Denki Sanyo Denki encoder ap13.6 diode DIODE MOTOROLA B34 l31c sanyo denki stepping tunnel diode General Electric ma 1.5 pfd
    Text: Data Sheet October 2001 ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC Introduction Agere Systems Inc. has developed a new ORCA Series 4 based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on


    Original     		PDF ORLI10G OIF-SFI4-01 16-bit DS01-277NCIP DS01-269NCIP) BL Super p5 sanyo denki BL SUPER P5 PLC Communication cables pin diagram Sanyo Denki Sanyo Denki encoder ap13.6 diode DIODE MOTOROLA B34 l31c sanyo denki stepping tunnel diode General Electric ma 1.5 pfd

    Sanyo Denki encoder

    Abstract: ORLI10G TRCV0110G TTRN0110G STM-16 chips 25LVD L30A
    Text: Preliminary Data Sheet March 2001 ORCA ORLI10G Field-Programmable System Chip 10 Gbits/s Transmit and Receive Line Interface Introduction Agere Systems Inc has developed a new ORCA Series 4 based FPSC, which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series


    Original     		PDF ORLI10G 16-bit DS01-073NCIP DS00-406FPGA) Sanyo Denki encoder TRCV0110G TTRN0110G STM-16 chips 25LVD L30A