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Cypress Semiconductor CY7C1318KV18-300BZXC NO WARRANTY
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DigiKey	CY7C1318KV18-300BZXC	Tray	1,597		1	1 $11.11 10 $11.11 100 $11.11 1000 $11.11 10000 $11.11	Buy Now
Cypress Semiconductor CY7C1315KV18-333BZC NO WARRANTY
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DigiKey	CY7C1315KV18-333BZC	Tray	142		1	1 $12.15 10 $12.15 100 $12.15 1000 $12.15 10000 $12.15	Buy Now
Cypress Semiconductor CY7C1318KV18-250BZXI NO WARRANTY
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DigiKey	CY7C1318KV18-250BZXI	Tray	130		1	1 $8.76 10 $8.76 100 $8.76 1000 $8.76 10000 $8.76	Buy Now
Infineon Technologies AG CY7C1314KV18-250BZXC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1314KV18-250BZXC	Tray	126		1	1 $31.91 10 $28.316 100 $26.347 1000 $23.84099 10000 $23.84099	Buy Now
Mouser Electronics	CY7C1314KV18-250BZXC		53			1 $31.91 10 $28.32 100 $24.7 1000 $23.18 10000 $23.18	Buy Now
Cypress Semiconductor CY7C1314KV18-250BZC NO WARRANTY
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1314KV18-250BZC	Tray	116		1	1 $8.79 10 $8.79 100 $8.79 1000 $8.79 10000 $8.79	Buy Now
Bristol Electronics	CY7C1314KV18-250BZC		17		1	1 $18 10 $18 100 $18 1000 $18 10000 $18	Buy Now
Flip Electronics	CY7C1314KV18-250BZC		5,308			1 - 10 - 100 - 1000 - 10000 -	Get Quote

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CY7C131 Datasheets (369)

Part	Manufacturer	Description	Datasheet Type	PDF
CY7C131	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF
CY7C131	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF
CY7C1310AV18	Cypress Semiconductor	18-Mb QDR -II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1310AV18-133BZC	Cypress Semiconductor	18-Mb QDR -II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1310AV18-167BZC	Cypress Semiconductor	18-Mb QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1310BV18	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1310BV18	Cypress Semiconductor	18-Mbit QDR-II SRAM 2 Word Burst Architecture	Original	PDF
CY7C1310BV18-167BZC	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1310BV18-167BZXC	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1310BV18-200BZC	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1310BV18-250BZC	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1310CV18	Cypress Semiconductor	18-Mbit QDR-II SRAM 2-Word Burst Architecture	Original	PDF
CY7C1310V18	Cypress Semiconductor	18-Mb QDR-II SRAM Two-word Burst Architecture	Original	PDF
CY7C1310V18-133BZC	Cypress Semiconductor	18-Mb SRAM two-word burst architecture, 133MHz	Original	PDF

CY7C1310V18-167BZC	Cypress Semiconductor	18-Mb SRAM two-word burst architecture, 167MHz	Original	PDF
CY7C1310V18-200BZC	Cypress Semiconductor	18-Mb SRAM two-word burst architecture, 200MHz	Original	PDF
CY7C131-15JC	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF
CY7C131-15JCT	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF
CY7C131-15JXC	Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 8KBIT 15NS 52PLCC	Original	PDF
CY7C131-15JXCT	Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 8KBIT 15NS 52PLCC	Original	PDF

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CY7C131 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth	Original	CY7C1319KV18/CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz CY7C1321KV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18	Original	18-Mbit CY7C1312KV18, CY7C1314KV18 CY7C1312KV18	PDF
7N19 Abstract: CY7C1316AV18 CY7C1318AV18 CY7C1320AV18 Text: CY7C1316AV18 CY7C1318AV18 CY7C1320AV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mb density 2M x 8, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate (DDR) interfaces (data transferred at	Original	CY7C1316AV18 CY7C1318AV18 CY7C1320AV18 18-Mbit 18-Mb 250-MHz CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 7N19 CY7C1316AV18 CY7C1318AV18 CY7C1320AV18	PDF
CY7C1316BV18 Abstract: CY7C1318BV18 CY7C1320BV18 CY7C1916BV18 Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 PRELIMINARY 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 250-MHz CY7C1316BV18 CY7C1318BV18 CY7C1320BV18 CY7C1916BV18	PDF
CY7C1310V18 Abstract: CY7C1312V18 CY7C1314V18 Text: 310V18 CY7C1310V18 CY7C1312V18 CY7C1314V18 ADVANCE INFORMATION 18-Mb 2-Word Burst SRAM with QDR -II Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250 MHz Clock for High Bandwidth	Original	310V18 CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb CY7C1310V18/CY7C1312V18/CY7C1314V18 CY7C1310V18 CY7C1312V18 CY7C1314V18	PDF
CY7C1310AV18 Abstract: CY7C1312AV18 CY7C1314AV18 Text: CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses	Original	CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 18-Mb 167-MHz 167MHz CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 CY7C1310AV18 CY7C1312AV18 CY7C1314AV18	PDF
PLCC-52 Abstract: CY7C130 CY7C131 CY7C140 CY7C141 CY7C131-25JC CY7C131-35J Z1014 Text: CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1K x 8 organization ■ 0.65 micron CMOS for optimum speed and power	Original	CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 CY7C130/130A/CY7C131/131A/CY7C140 CY7C130/130A/ CY7C131/131A PLCC-52 CY7C130 CY7C131 CY7C140 CY7C141 CY7C131-25JC CY7C131-35J Z1014	PDF
CY7C1311CV18 Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18 Text: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR -II SRAM 2 Word Burst Architecture Features Functional Description Separate Independent read and write data ports ❐ Supports concurrent transactions • 250 MHz clock for high bandwidth ■ 2 Word Burst on all accesses	Original	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, CY7C1314BV18 CY7C1310BV18 CY7C1312BV18 CY7C1910BV18	PDF
CY7C1311BV18 Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth	Original	CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18	PDF
7C13135 Abstract: CY7C140-35PC 7C130 CY7C130 CY7C131 CY7C140 CY7C141 Text: CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports	Original	CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131/CY7C140 CY7C141 CY7C130/ CY7C131 CY7C140/CY7C141 16-bit 7C13135 CY7C140-35PC 7C130 CY7C130 CY7C140	PDF
Untitled Abstract: No abstract text available Text: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310KV18 – 2 M x 8 ■ 333 MHz clock for high bandwidth	Original	18-Mbit CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 CY7C1310KV18 CY7C1910KV18 CY7C1312KV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit 300-MHz	PDF
Untitled Abstract: No abstract text available Text: CY7C1317V18 CY7C1319V18 CY7C1321V18 PRELIMINARY 18-Mb DDR -II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mb density 2M x 8, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency	Original	CY7C1317V18 CY7C1319V18 CY7C1321V18 18-Mb 250-MHz p19V18/CY7C1321V18 BB165D BB165A	PDF

Untitled Abstract: No abstract text available Text: CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • QDR-II operates with 1.5 cycle read latency when the DLL is enabled	Original	CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 18-Mbit 300-MHz 600MHz)	PDF
Untitled Abstract: No abstract text available Text: CY7C1317BV18 CY7C1319BV18 CY7C1321BV18 PRELIMINARY 18-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM	Original	CY7C1317BV18 CY7C1319BV18 CY7C1321BV18 18-Mbit 300-MHz 600MHz) CY7C1917BV18 BB165E	PDF
Untitled Abstract: No abstract text available Text: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions	Original	CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit CY7C1310KV18 CY7C1312KV18	PDF
CY7C1311V18 Abstract: CY7C1313V18 CY7C1315V18 Text: CY7C1311V18 CY7C1313V18 CY7C1315V18 PRELIMINARY 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • Four-word Burst for reducing address bus frequency	Original	CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mb 250-MHz CY7C1311V18/CY7C1313V18/CY7C1315V18 CY7C1311V18 CY7C1313V18 CY7C1315V18	PDF
CY7C Abstract: CY7C130 CY7C131 CY7C140 CY7C141 Text: CY7C130, CY7C130A CY7C131, CY7C131A 1 K x 8 Dual-Port Static RAM 1 K × 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K × 8 organization ■ 0.65 micron CMOS for optimum speed and power	Original	CY7C130, CY7C130A CY7C131, CY7C131A CY7C130/130A/CY7C131/131A/CY7C140 CY7C141 CY7C130/130A/CY7C131/131A CY7C CY7C130 CY7C131 CY7C140 CY7C141	PDF
3N50 Abstract: CY7C1311V18 CY7C1313V18 CY7C1315V18 Text: CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency	Original	CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mbit 250-MHz 3N50 CY7C1311V18 CY7C1313V18 CY7C1315V18	PDF
cy7c131-55nc Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140 Text: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex	OCR Scan	CY7C130/CY7C131 CY7C140/CY7C141 CY7C140/ CY7C141 CY7C130/ CY7C131; IDT7130 IDT7140 cy7c131-55nc ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7140	PDF
ebe switches Abstract: CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35 Text: CYPRESS SEMICONDUCTOR 00 0 3 4 2 1 EbE D 5 • CY7C130/CY7C131 CY7C140/CY7C141 -Z Z A Z . o y n p rrQ C 1024 x 8 Dual-Port Static RAM SEMICONDUCTOR Features Functional Description • 0,8-micron CMOS for optimum speed/power • Automatic power-down • TTL-compatible	OCR Scan	CY7C130/CY7C131 CY7C140/CY7C141 20O1V CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C130/CY7C131/CY7C140/ ebe switches CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35	PDF
Untitled Abstract: No abstract text available Text: CY7C130/CY7C131 CY7C140/CY7C141 CYPRESS SEMICONDUCTOR Features Functional Description • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable of withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation	OCR Scan	CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131 CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C130/CY 7C131/CY7C140/	PDF
Untitled Abstract: No abstract text available Text: fax id: 5200 CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS 1K x 8 Dual-Port Static Ram Features Functional Description True Dual-Ported memory cells which allow simulta neous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power	OCR Scan	130/C 140/C 65-micron CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin	PDF

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CY7C131 Search Results

CY7C131 Price and Stock

Cypress Semiconductor CY7C1318KV18-300BZXC

Cypress Semiconductor CY7C1315KV18-333BZC

Cypress Semiconductor CY7C1318KV18-250BZXI

Infineon Technologies AG CY7C1314KV18-250BZXC

Cypress Semiconductor CY7C1314KV18-250BZC

CY7C131 Datasheets (369)

CY7C131 Datasheets Context Search

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7N19

CY7C1316BV18

CY7C1310V18

CY7C1310AV18

PLCC-52

CY7C1311CV18

CY7C1310BV18

CY7C1311BV18

7C13135

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CY7C1311V18

CY7C

3N50

cy7c131-55nc

ebe switches

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