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    CY7C1311CV18 Search Results

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    CY7C1311CV18 Price and Stock

    Rochester Electronics LLC CY7C1311CV18-250BZC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1311CV18-250BZC Tray 309 9
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    Rochester Electronics LLC CY7C1311CV18-200BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1311CV18-200BZC Tray 190 10
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    Infineon Technologies AG CY7C1311CV18-200BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    Avnet Americas CY7C1311CV18-200BZC Tray 4 Weeks 12
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    Infineon Technologies AG CY7C1311CV18-250BZC

    IC SRAM 18MBIT PAR 165FBGA
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    Avnet Americas CY7C1311CV18-250BZC Tray 4 Weeks 11
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    Cypress Semiconductor CY7C1311CV18-200BZC

    QDR SRAM, 2MX8, 0.45ns, CMOS, PBGA165 '
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    Rochester Electronics CY7C1311CV18-200BZC 190 1
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    CY7C1311CV18 Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1311CV18 Cypress Semiconductor 18-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1311CV18-200BZC Cypress Semiconductor 18-Mbit QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1311CV18-250BZC Cypress Semiconductor 18-Mbit QDR -II SRAM 4-Word Burst Architecture Original PDF

    CY7C1311CV18 Datasheets Context Search

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    CY7C1311CV18

    Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
    Text: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original     		PDF CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • QDR-II operates with 1.5 cycle read latency when the DLL is enabled


    Original     		PDF CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 18-Mbit 300-MHz 600MHz)

    CY7C1311CV18

    Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
    Text: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original     		PDF CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-07165 Spec Title: 7C1313CV18/CY7C1315CV18, 18-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture


    Original     		PDF 7C1313CV18/CY7C1315CV18, 18-MBIT CY7C1313CV18 CY7C1315CV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1313CV18 – 1M x 18 •


    Original     		PDF CY7C1313CV18 CY7C1315CV18 18-Mbit CY7C1313CV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1313CV18 – 1M x 18 ■ 300 MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency


    Original     		PDF CY7C1313CV18 CY7C1315CV18 18-Mbit CY7C1313CV18