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    CY7C1314V18 Search Results

    CY7C1314V18 Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1314V18 Cypress Semiconductor 18-Mb QDR-II SRAM Two-word Burst Architecture Original PDF
    CY7C1314V18-133BZC Cypress Semiconductor 18-Mb SRAM two-word burst architecture, 133MHz Original PDF
    CY7C1314V18-167BZC Cypress Semiconductor 18-Mb SRAM two-word burst architecture, 167MHz Original PDF
    CY7C1314V18-200BZC Cypress Semiconductor 18-Mb SRAM two-word burst architecture, 200MHz Original PDF

    CY7C1314V18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CY7C1310V18

    Abstract: CY7C1312V18 CY7C1314V18
    Text: 310V18 CY7C1310V18 CY7C1312V18 CY7C1314V18 ADVANCE INFORMATION 18-Mb 2-Word Burst SRAM with QDR -II Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250 MHz Clock for High Bandwidth


    Original     		PDF 310V18 CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb CY7C1310V18/CY7C1312V18/CY7C1314V18 CY7C1310V18 CY7C1312V18 CY7C1314V18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1310V18 CY7C1312V18 CY7C1314V18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses


    Original     		PDF CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb 167-MHz 167MHz

    CY7C1310V18

    Abstract: CY7C1312V18 CY7C1314V18
    Text: CY7C1310V18 CY7C1312V18 CY7C1314V18 PRELIMINARY 18-Mb QDR -II SRAM Two-word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth • Two-word Burst on all accesses


    Original     		PDF CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb 167-MHz 167MHz CY7C1310V18/CY7C1312V18/CY7C1314V18 CY7C1310V18 CY7C1312V18 CY7C1314V18

    CY7C1312V18

    Abstract: CY7C1312V18-133BZC CY7C1312V18-167BZC CY7C1314V18 CY7C1314V18-133BZC CY7C1314V18-167BZC
    Text: CY7C1312V18 CY7C1314V18 CONFIDENTIAL Errata Revision: [*] 11/14/03 Errata Document for CY7C1312V18 & CY7C1314V18 This document describes errata for the CY7C1312V18 and CY7C1314V18. Details include errata trigger conditions, available workarounds, and silicon revision applicability. This document should be used as a suplement to the


    Original     		PDF CY7C1312V18 CY7C1314V18 CY7C1312V18 CY7C1314V18. CY7C1312V18-133BZC CY7C1312V18-167BZC CY7C1314V18-133BZC CY7C1314V1tent CY7C1312V18-133BZC CY7C1312V18-167BZC CY7C1314V18 CY7C1314V18-133BZC CY7C1314V18-167BZC

    CY7C1310BV18

    Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 static SRAM single port
    Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • Core VDD = 1.8V ±0.1V ; I/O VDDQ = 1.4V to VDD The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and


    Original     		PDF CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, CY7C1314BV18 CY7C1310BV18 CY7C1312BV18 CY7C1910BV18 static SRAM single port