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    74HC11 Search Results

    74HC11 Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    74HC11FPEL-E Renesas Electronics Corporation HD/RD74HC Series Visit Renesas Electronics Corporation
    74HC112TELL-E Renesas Electronics Corporation HD/RD74HC Series, , / Visit Renesas Electronics Corporation
    74HC112FPEL-E Renesas Electronics Corporation HD/RD74HC Series Visit Renesas Electronics Corporation
    74HC112P-E Renesas Electronics Corporation HD/RD74HC Series Visit Renesas Electronics Corporation
    74HC11P-E Renesas Electronics Corporation HD/RD74HC Series Visit Renesas Electronics Corporation
    SN74HC11NSR Texas Instruments Triple 3-Input Positive-AND Gates 14-SO -40 to 85 Visit Texas Instruments Buy
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    74HC11 Price and Stock

    Rochester Electronics LLC 74HC112D,652

    NEXPERIA 74HC112D - J-K FLIP-FLO
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    DigiKey 74HC112D,652 Bulk 22,710 1,337
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    Rochester Electronics LLC 74HC11DB,112

    IC GATE AND
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    DigiKey 74HC11DB,112 Bulk 6,162 1,610
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    74HC11DB,112 Bulk 3,432 1,610
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    Texas Instruments CD74HC11M96

    IC GATE AND 3CH 3-INP 14SOIC
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    Bristol Electronics CD74HC11M96 2,291
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    Rochester Electronics CD74HC11M96 11,880 1
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    onsemi MC74HC11ADTR2G

    IC GATE AND 3CH 3-INP 14TSSOP
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    MC74HC11ADTR2G Cut Tape 2,455 1
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    New Advantage Corporation MC74HC11ADTR2G 2,500 1
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    Texas Instruments SN74HC11ANSR

    IC GATE AND 3CH 3-INP 14SO
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    DigiKey SN74HC11ANSR Cut Tape 1,996 1
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    Find more 74HC11 price and stock on Findchips.com

    74HC11 Datasheets (61)

    Part ECAD Model Manufacturer Description Curated Type PDF
    74HC11 Philips Semiconductors Triple 3-Input AND Gate Original PDF
    74HC112 Philips Semiconductors Negative-edge trigger Original PDF
    74HC112D Philips Semiconductors dual JK flip-flop with set and reset negative-edge trigger Original PDF
    74HC112D Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC112D,652 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Bulk Pack, CECC Original PDF
    74HC112D,653 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13", CECC Original PDF
    74HC112DB Philips Semiconductors dual JK flip-flop with set and reset negative-edge trigger Original PDF
    74HC112DB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC112DB,112 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Tube Original PDF
    74HC112DB,118 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13" Original PDF
    74HC112DB-T NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V Original PDF
    74HC112DB-T Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC112D-T NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V Original PDF
    74HC112D-T Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC112N Philips Semiconductors dual JK flip-flop with set and reset negative-edge trigger Original PDF
    74HC112N Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC112N,652 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT38-4 (DIP16); Container: Bulk Pack, CECC Original PDF
    74HC112PW Philips Semiconductors dual JK flip-flop with set and reset negative-edge trigger Original PDF
    74HC112PW Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HC112PW,112 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger ; Fmax: 66 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 17@5V ns; Voltage: 2.0-6.0 V; Package: SOT403-1 (TSSOP16); Container: Tube Original PDF

    74HC11 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    IC 74HC112

    Abstract: 74HC112
    Text: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141A Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2000


    Original     		PDF CD54/74HC112, CD54/74HCT112 SCHS141A HC112 HCT112 loSZZU001B, SDYU001N, SCET004, SCAU001A, CD74HC112E IC 74HC112 74HC112

    74hc11

    Abstract: No abstract text available
    Text: 74HC11; 74HCT11 Triple 3-input AND gate Rev. 5 — 16 December 2011 Product data sheet 1. General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .


    Original     		PDF 74HC11; 74HCT11 74HCT11 74HC11: 74HCT11: JESD22-A114F JESD22-A115-A 74hc11

    74HCT11

    Abstract: 74hc11
    Text: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54/74HC11, CD54/74HCT11 Data sheet acquired from Harris Semiconductor SCHS273A High Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs


    Original     		PDF CD54/74HC11, CD54/74HCT11 SCHS273A HCT11 SDYA012 SN54/74HCT SCLA011 SCLA008 SZZU001B, SDYU001N, 74HCT11 74hc11

    74hc11

    Abstract: No abstract text available
    Text: 74HC11-Q100; 74HCT11-Q100 Triple 3-input AND gate Rev. 2 — 22 March 2013 Product data sheet 1. General description The 74HC11-Q100; 74HCT11-Q100 is a triple 3-input AND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in


    Original     		PDF 74HC11-Q100; 74HCT11-Q100 74HCT11-Q100 AEC-Q100 74HC11-Q100: 74HCT11-Q100: 74hc11

    74HC112

    Abstract: data sheet IC 74HC112 CD54HC112F3A CD54HCT112F3A CD74HC112E CD74HC112NSR
    Text: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141B Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised March 2002


    Original     		PDF HC112 HCT11 CD54/74HC112, CD54/74HCT112 SCHS141B HC112 HCT112 74HC112 data sheet IC 74HC112 CD54HC112F3A CD54HCT112F3A CD74HC112E CD74HC112NSR

    HCT114

    Abstract: 74HC11 datasheet 74hc11 74HC11D 74HC11DB 74HC11N 74HCT11 74HCT11D 74HCT11DB 74HCT11N
    Text: 74HC11; 74HCT11 Triple 3-input AND gate Rev. 04 — 25 March 2010 Product data sheet 1. General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .


    Original     		PDF 74HC11; 74HCT11 74HCT11 74HC11: 74HCT11: JESD22-A114F JESD22-A115-A HCT114 74HC11 datasheet 74hc11 74HC11D 74HC11DB 74HC11N 74HCT11D 74HCT11DB 74HCT11N

    74HC11

    Abstract: 74HCT11 74HC11D 74HC11N 74HCT11D 74HCT11DB 74HCT11N 74HC11DB 74HCT11N pin diagram 74HCT11P
    Text: 74HC11; 74HCT11 Triple 3-input AND gate Rev. 03 — 9 February 2010 Product data sheet 1. General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .


    Original     		PDF 74HC11; 74HCT11 74HCT11 74HC11: 74HCT11: JESD22-A114F JESD22-A115-A 74HC11 74HC11D 74HC11N 74HCT11D 74HCT11DB 74HCT11N 74HC11DB 74HCT11N pin diagram 74HCT11P

    74ls112 pin diagram

    Abstract: 74HC112
    Text: GD54/74HC112, GD54/74HCT112 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 54/74LS112. They consist of two J-K flip-flops with individual J, K, CLOCK, PRESET, and CLEAR in­ puts. These flip-flops are edge sensitive to the clock


    OCR Scan     		PDF GD54/74HC112, GD54/74HCT112 54/74LS112. 74ls112 pin diagram 74HC112

    74HC11A

    Abstract: 74HC11
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC11 Triple 3-In p u t A N D Gate High-Performance Silicon-Gate CMOS The MC54/74HC11 is identical in pinout to the LS11, The device inputs are com ­ patible w ith standard CMOS outputs; w ith pullup resistors, they are com patible w ith


    OCR Scan     		PDF MC54/74HC11 74HC11A 74HC11

    74hct11m

    Abstract: 74hc11
    Text: Technical Data CD54/74HC11 CD54/74HCT11 File N um ber 1475 High-Speed CMOS Logic Triple 3-Input AND Gate Type Features: • B utte red inpu ts ■ Typical propagation delay = 8 ns @ VCc - 5 V, CL = 15 pF, 7« = 25° C T E R M IN A L A S S IG N M E N T The R C A-CD54/74HC11 and C D 54/74HCT11 lo gic gates


    OCR Scan     		PDF CD54/74HC11 CD54/74HCT11 -CD54/74HC11 54/74HCT11 54LS/74LS CD54HC11 CD54HCT11 92CS-36 972R5 54/74H 74hct11m 74hc11

    JK flip flop IC

    Abstract: J-K Flip flops 4000B 74LS113 M74HC113 M74HC113P "J-K Flip flops"
    Text: M IT S U B IS H I HIGH S P E E D C M O S sc< M 74HC113P s v x n.>A'C D U A L J -K F L IP -F L O P W IT H S E T DESCRIPTION The M 74H C 113 is a sem iconductor integrated circu it con­ PIN CONFIGURATION TOP VIEW sisting of tw o n e g a tiv e -e d g e trig g e re d J-K flip flops w ith in­


    OCR Scan     		PDF M74HC113P M74HC113 50MHz 10/zW/package JK flip flop IC J-K Flip flops 4000B 74LS113 M74HC113P "J-K Flip flops"

    74HC113

    Abstract: MC74HCXXXN S-10
    Text: MOTOROLA SE M IC O N D U C TO R TECHNICAL DATA MC54/74HC113 D u a l J -K F lip -F lo p w ith S e t High-Performance Silicon-Gate CM O S J SUFFIX CERAMIC CASE 632-08 T h e M C 5 4 / 7 4 H C 1 13 is id e n tic a l in p in o u t t o th e L S 1 1 3 . T h e d e v ic e in p u ts a re


    OCR Scan     		PDF MC54/74HC113 K1-80 74HC113 MC74HCXXXN S-10

    74hc11

    Abstract: No abstract text available
    Text: \ - + Technical Data CD54/74HC11 CD54/74HCT11 HARRIS SEMICOND 3 -2- 1-00 File N um b er SECTOR 27E D H 4302271 1475 001747= 2 • H A S High-Speed CMOS Logic Triple 3-Input AND Gate Type Features: ■ B uffe red inputs m Typical propagation delay = 8 ns r A = 25° c


    OCR Scan     		PDF CD54/74HC11 CD54/74HCT11 -CD54/74HC11 CD54/74HCT11 T/74H 54/74HC 54/74HCT 74hc11

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC113 Dual J-K Flip-Flop w ith Set H igh-Perform ance S ilico n -G ate C M O S The M C 5 4 /7 4 H C 1 13 is id entical in p in o u t to th e L S 1 13. T he device in p u ts are co m p a tib le w ith standard C M O S o u tp u ts ; w ith pullup resistors, th e y are c o m p a tib le


    OCR Scan     		PDF MC54/74HC113

    MC54HC112

    Abstract: No abstract text available
    Text: MOTOROLA • SEMICONDUCTOR TECHNICAL DATA MC54/74HC112 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS The M C 54/74H C 11 2 is id entical in p in o u t to the LS112. The device in p u ts are c o m p a tib le w ith standard C M O S o u tp u ts ; w ith p u llu p resistors, th e y are c o m p a tib le


    OCR Scan     		PDF MC54/74HC112 MC54HC112 MC74HC112 LS112. HC112

    74ls112 pin diagram

    Abstract: No abstract text available
    Text: TOSHIBA LOG IC/MEMOR Y IME 0 I ^0 1 724 0 0 0 1 0 0 3 0 o| — 74HC112P/F TC 74HC112P/F DUAL J-K FLIP FLOP WITH PRESET AND CLEAR The 74HC112 is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2M0S technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining


    OCR Scan     		PDF TC74HC112P/F 74HC112P/F TC74HC112 TC74H C112P/F 74ls112 pin diagram

    GD74HC11

    Abstract: No abstract text available
    Text: GD54/74HC11, GD54/74HCT11 TRIPLE 3-INPUT AND GATES General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 1 . They contain three independent 3-input AND gates. These devices are characteriz­ ed for operation over wide temperature ranges to


    OCR Scan     		PDF GD54/74HC11, GD54/74HCT11 GD74HC11

    74hc113

    Abstract: 74HCT113 GD74HCT11 74HC GD54HC113 GD74HC113 74LS113
    Text: GD54/74HC113, GD54/74HCT113 DUAL J-K FLIP-FLOPS WITH PRESET General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 13. They consist of two J-K flip-flops with individual J, K, Clock, and Preset inputs. These flip-flops are edge sensitive to the clock input and


    OCR Scan     		PDF GD54/74HC113, GD54/74HCT113 54/74LS113. 74hc113 74HCT113 GD74HCT11 74HC GD54HC113 GD74HC113 74LS113

    74HC112

    Abstract: No abstract text available
    Text: • MOTOROLA SEMICONDUCTOR M TECHNICAL DATA IH0T4 blE D b3b75se OCHITHO 3b4 otorola se clogic MC54/74HC112 Dual J -K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620*09 High-Performance Silicon-Gate CMOS T he M C 54/74H C 11 2 is id en tic a l in p in o u t to th e L S 112. T he device in p u ts are


    OCR Scan     		PDF b3b75se MC54/74HC112 54/74H HC112 b3b72S2 74HC112

    Untitled

    Abstract: No abstract text available
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC113 Dual J-K Flip-Flop w ith Set High-Performance Silicon-Gate CM OS J SUFFIX CERAMIC CASE 632-08 T h e M C 5 4 /7 4 H C 1 1 3 is id e n tic a l in p in o u t to th e L S 113. T h e d e v ic e in p u ts a re [f 1 II u u


    OCR Scan     		PDF MC54/74HC113 MC54/74HC113

    LM 4017 decade counter driver

    Abstract: 74HC7244A 74HCT7007A 74HC11A 74HC85A 74HC147 decimal to binary encoder cmos 4008 74HC21A 74HC07A 74HC7244
    Text: 2.H IG H SPEED CMOS SELECTION GUIDE NÄ N D NOR A ND OR IN V E R T E R ,B U F FE R 74HC00A 74HCT00A 74HC03A 74HC10A 74HC20A 74HC30 71HC132A 74HC133A GATE 74HC02A 74HCT02A 74HC27A 74HC4002A 74HC4078 74HC08A 74HCT08A 74HC09A 74HC11A 74HC21A 74HC32A 74HCT32A 74HC4072


    OCR Scan     		PDF 74HC00A 74HCT00A 74HC03A 74HC10A 74HC20A 74HC30 71HC132A 74HC133A 74HC02A 74HCT02A LM 4017 decade counter driver 74HC7244A 74HCT7007A 74HC11A 74HC85A 74HC147 decimal to binary encoder cmos 4008 74HC21A 74HC07A 74HC7244

    Untitled

    Abstract: No abstract text available
    Text: Technical Data CD54/74HC11 CD54/74HCT11 File N um ber 1475 High-Speed CMOS Logic Triple 3-Input AND Gate Type Features: • B u ffe re d inputs ■ Typical propagation delay - 8 ns < ' Vcc = 5 V , C L = 15 pF, 7a = 25° C T E R M IN A L A S S IG N M E N T


    OCR Scan     		PDF CD54/74HC11 CD54/74HCT11 54/74H 54/74HCT11 T/74H 54LS/74LS CD54HC11 CD54HCT1 92CS-36972R5 54/74HC

    74HC114

    Abstract: No abstract text available
    Text: SN 54HC114, SN 74HC114 DUAL J K NEGATIVE EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR. AND COMMON CLOCK D2684, DECEMBER 1982-REVISED SEPTEMBER 1987 c lr C C2 l j[ 3 ip r e C 4 iq C 5 iq C 6 gndC ik Dependable Texas Instrum ents Quality and Reliability


    OCR Scan     		PDF 54HC114, 74HC114 D2684, 1982-REVISED 300-mil SN54HC114. SN74HC114 SN54HC114 SN74HC114

    74hc11

    Abstract: 74HC11A
    Text: MOTOROLA H SE M IC O N D U C T O R TECHNICAL DATA MC54/74HC11 Triple 3-Input A N D Gate High-Performance Silicon-Gate C M O S J SU F F IX C E R A M IC C A S E 632-08 The MC54/74HC11 is identical in pinout to the LS11. The device inputs are com­ patible with standard C M O S outputs; with pullup resistors, they are compatible with


    OCR Scan     		PDF MC54/74HC11 74hc11 74HC11A