74HCT11
Philips Semiconductors
Triple 3-Input AND Gate
Original
PDF
74HCT112
Philips Semiconductors
negative-edge trigger
Original
PDF
74HCT112D
Philips Semiconductors
dual JK flip-flop with set and reset negative-edge trigger
Original
PDF
74HCT112D
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HCT112D,652
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax : 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT109-1 (SO16); Container: Bulk Pack, CECC
Original
PDF
74HCT112D,653
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax : 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13", CECC
Original
PDF
74HCT112DB
Philips Semiconductors
dual JK flip-flop with set and reset negative-edge trigger
Original
PDF
74HCT112DB
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HCT112DB,112
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax : 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT338-1 (SSOP16); Container: Tube
Original
PDF
74HCT112DB,118
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax : 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13"
Original
PDF
74HCT112DB-T
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax : 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V
Original
PDF
74HCT112DB-T
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HCT112D-T
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax : 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V
Original
PDF
74HCT112D-T
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HCT112N
Philips Semiconductors
Dual JK flip-flop with set and reset, negative-edge trigger
Original
PDF
74HCT112N
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HCT112N,652
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax : 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT38-4 (DIP16); Container: Bulk Pack, CECC
Original
PDF
74HCT112PW
Philips Semiconductors
dual JK flip-flop with set and reset negative-edge trigger
Original
PDF
74HCT112PW
Unknown
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project.
Historical
PDF
74HCT112PW,112
NXP Semiconductors
dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax : 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT403-1 (TSSOP16); Container: Tube
Original
PDF