Untitled
Abstract: No abstract text available
Text: Datasheet Secondary power supply series for automotive 2.69 to 5.5V, 1.2V Output, 2.25MHz Synchronous Step-Down Converter BD90571EFJ-C ●General Description The BD90571EFJ-C is a synchronous rectification type step-down DC/DC converter with a 2.25MHz fixed
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25MHz
BD90571EFJ-C
BD90571EFJ-C
25MHz
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MSC2323258D
Abstract: No abstract text available
Text: This version: Mar. 3. 1999 Semiconductor MSC2323258D-xxBS4/DS4 2,097,152-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSC2323258D-xxBS4/DS4 is a fully decoded, 2,097,152-word x 32-bit CMOS dynamic random access memory module composed of four 16Mb DRAMs in SOJ packages mounted with eight decoupling capacitors on a
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MSC2323258D-xxBS4/DS4
152-word
32-bit
MSC2323258D-xxBS4/DS4
72-pin
MSC2323258D
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MSC23B236D
Abstract: No abstract text available
Text: This version: Mar. 3. 1999 Semiconductor MSC23B236D-xxBS8/DS8 2,097,152-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The MSC23B236D-xxBS8/DS8 is a fully decoded, 2,097,152-word x 36-bit CMOS dynamic random access memory module composed of four 16Mb DRAMs in SOJ packages and four 2Mb DRAMs in SOJ packages mounted with
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MSC23B236D-xxBS8/DS8
152-word
36-bit
MSC23B236D-xxBS8/DS8
72-pin
MSC23B236D
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642006EGM1G09TD
Abstract: DIMM 1998
Text: 2M x 64 Bit 3.3V UNBUFFERED EDO DIMM Extended Data Out EDO DRAM DIMM 642006EGM1G09TD 168 Pin 2Mx64 EDO DIMM Unbuffered, 1k Refresh, 3.3V with SPD Pin Assignment Pin# General Description The module is a 2Mx64 bit, 9 chip, 3.3V, 168 Pin DIMM module consisting of (8) 1Mx16 (TSOP) DRAM
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642006EGM1G09TD
2Mx64
DS390-1
DIMM 1998
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95051
Abstract: No abstract text available
Text: G -LINK GLT440L08 512K X 8 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Oct 2001 Rev.2.0 Features : Description : ∗ ∗ ∗ The GLT440L08 is a 524,288 x 8 bit highperformance CMOS dynamic random access memory. The GLT440L08 offers Fast Page mode with Extended Data Output has asymmetric address
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GLT440L08
GLT440L08
1024-cycle
Current-160mA
300mil
330mil
445mil
400mil
95051
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Untitled
Abstract: No abstract text available
Text: HY51V S 16163HG/HGL 1M x 16Bit EDO DRAM PRELIMINARY DESCRIPTION The HY51V(S)16163HG/HGL is the new generation dynamic RAM organized 1,048,576 words x 16bit. HY51V(S)16163HG/HGL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The HY51V(S)16163HG/HGL offers Extended Data Out PageMode as a high speed access mode. Multiplexed address inputs permit the HY51V(S)16163HG/HGL to be
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HY51V
16163HG/HGL
16Bit
16163HG/HGL
16bit.
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Untitled
Abstract: No abstract text available
Text: G -LINK GLT440M04 1M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Apr. 2002 Rev. 2.2 Features : Description : ∗ ∗ ∗ ∗ The GLT440M04 is a high-performance CMOS dynamic random access memory containing 4,194,304 bits organized in a x4 configuration. The GLT440M04 offers page
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GLT440M04
GLT440M04
1024-cycle
-Onl08-15T
128Kx8
300mil
GLT44016-40J4
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MSC23140D
Abstract: DS1067
Text: This version: Feb. 23. 1999 Semiconductor MSC23140D-xxBS10/DS10 1,048,576-word x 40-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The MSC23140D-xxBS10/DS10 is a fully decoded, 1,048,576-word x 40-bit CMOS dynamic random access memory module composed of ten 4Mb DRAMs in SOJ packages mounted with ten decoupling capacitors on a 72pin glass epoxy single-inline package. This module supports any application where high density and large capacity
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MSC23140D-xxBS10/DS10
576-word
40-bit
MSC23140D-xxBS10/DS10
72pin
72-pin
MSC23140D
DS1067
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Untitled
Abstract: No abstract text available
Text: K7R323684C K7R321884C K7R320984C Preliminary TM 1Mx36, 2Mx18 & 4Mx9 QDR II b4 SRAM 36Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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K7R323684C
K7R321884C
K7R320984C
1Mx36,
2Mx18
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ieee1149.1 cypress
Abstract: P-LBGA165-15x17-1
Text: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid
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JTAG 10P
Abstract: K7R641882M-FC25 K7R640982M-FC25 K7R643682M-FC20
Text: K7R643682M K7R641882M K7R640982M Preliminary 2Mx36 & 4Mx18 & 8Mx9 QDRTM II b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit, 8Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Sep, 14 2002 Advance 0.1 1. Update AC timing characteristics.
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K7R643682M
K7R641882M
K7R640982M
2Mx36
4Mx18
2Mx36-bit,
4Mx18-bit,
K7R640982M
JTAG 10P
K7R641882M-FC25
K7R640982M-FC25
K7R643682M-FC20
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Untitled
Abstract: No abstract text available
Text: K7I323684C K7I321884C Preliminary 1Mx36 & 2Mx18 DDRII CIO b4 SRAM 36Mb DDRII SRAM Specification 165 FBGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
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K7I323684C
K7I321884C
1Mx36
2Mx18
11x15
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Untitled
Abstract: No abstract text available
Text: K7J643682M K7J641882M Preliminary 2Mx36 & 4Mx18 DDR II SIO b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Mar. 9, 2003 Advance 0.1 1. Correct the JTAG ID register definition
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K7J643682M
K7J641882M
2Mx36
4Mx18
2Mx36-bit,
4Mx18-bit
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Untitled
Abstract: No abstract text available
Text: TMS44100, TMS44100P 4194304-BIT DYNAMIC RANDOM-ACCESS MEMORY SMHS410F-SEPTEMBER 1989-REVISED DECEMBER 1992 Single 5-V Power Supply ±10% Tolerance Performance Ranges: ACCESS ACCESS ACCESS SD P AC K A G E t (TOP VIEW) DJ P A C K A G E t (TOP VIEW) Organization . . . 4194 304 x 1
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TMS44100,
TMS44100P
4194304-BIT
SMHS410F-SEPTEMBER
1989-REVISED
TMS44100/P-60
TMS44100/P-70
TMS44100/P-80
A0-A10
TMS44100
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44-800-p
Abstract: 44800P PIN DIAGRAM of IC AD 524 IN2045
Text: TMS44800, TMS44800P 524 288-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORIES SMHS480B-AUGUST1992-REVISED DECEMBER 1992 This data sheet is applicable to all TMS44800/Ps symbolized with Revision“B" and subsequent revisions as described on page 22. * Organization . . . 524 288 x 8
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TMS44800,
TMS44800P
288-WORD
SMHS480B-AUGUST1992-REVISED
TMS44800/Ps
SMHS480B-AUQUST1992-REVISED
TMS44800J
44-800-p
44800P
PIN DIAGRAM of IC AD 524
IN2045
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TMS44410
Abstract: TMS44410-70
Text: TMS44410 1 048 576-WORD BY 4-BIT WRITE-PER-BIT DYNAMIC RANDOM-ACCESS MEMORY REV A - • Organization . . . 1 048 576 x 4 SMHS441 JANUARY 1991 DM and DJ Packaget Top View • Single 5-V Power Supply (±10% Tolerance) • Performance Ranges: ACCESS ACCESS ACCESS
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TMS44410
576-WORD
SMHS441
TMS44410-60
TMS44410-70
TMS44410-80
TMS44410-10
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TMS44101
Abstract: No abstract text available
Text: TMS44101 4194 304-BIT DYNAMIC RANDOM-ACCESS MEMORY REV A — SMHS411 — JA N U A R Y 1991 Organization . . . 4 194 304 x DC w C RAS C 1 1 ^ 2 3 Z 4 NC A 10 C 5 Single 5-V Power Supply ±10% Tolerance Performance Ranges: A0 C 9 A1 C 10 A2 C 11 READ ACCESS ACCESS ACCESS
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TMS44101
304-BIT
SMHS411
TMS44101s
TMS44101-60
TMS44101-10
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TS-2321
Abstract: No abstract text available
Text: SMJ44400 1 048 576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS041D - JANUARY 1991 - REVISED JUNE 1995 Processed to MIL-STD-883, Class B Organization. . . 1 048 576 x 4 Single 5-V Power Supply ±10% Tolerance Performance Ranges: A CCESS ACCESS A CCESS
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SMJ44400
576-WORD
SGMS041D
MIL-STD-883,
SMJ44400-80
SMJ44400-10
SMJ44400-12
TS-2321
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TMS44400
Abstract: TMS44400-10
Text: TMS44400 1 048 576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY R E V A — S M H S 4 4 0 B — O C T O B E R 1 9 8 9 — R E V IS E D J A N U A R Y 1991 DM AND DJ P acka ge st Top View This Data Sheet Is Applicable to A ll TMS44400s Symbolized With Revision “B" and Subsequent
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TMS44400
576-WORD
TMS44400s
TMS44400-60
TMS44400-70
TMS44400-80
TMS44400-10
SMHS440B
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marking WMM
Abstract: RA52 1cas5 22r29
Text: 1 MEG x 4 DRAM DRAM QUAD CAS PARITY, FAST PAGE MODE FEATURES • Four independent CAS controls, allowing individual m anipulation to each of the four data In p u t/O u tp u t ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit w ords w hen using 1 Meg x 4 DRAMs for mem ory
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225mW
1024-cycle
D01-4
T-46-23-17
MT4C4256DJ
MT4C4259EJ
marking WMM
RA52
1cas5
22r29
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S891C
Abstract: SS828
Text: TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY S M K S891C -A U G U S T 1996-R E V IS E D OCTOBER 1997 This data sheet is applicable to TMS418160As symbolized by Revision “E ” and subsequent revisions as described in the device symbolization section.
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TMS418160A
16-BIT
S891C
1996-R
TMS418160As
1024-Cycle
18160A-50
18160A-60
4181B0A-70
SS828
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Untitled
Abstract: No abstract text available
Text: HM5118160BI Series 1048576-word x 16-bit Dynamic Random Access Memory HITACHI ADE-203-580A Z Rev. 1.0 May. 20, 1996 Description T he H itachi H M 5118160B I is a C M O S dynam ic R A M organized as 1,048,576-w ord x 16-bit. It em ploys the m ost advanced C M O S technology fo r high perform ance and low pow er. T he H M 5118160B I offers
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HM5118160BI
1048576-word
16-bit
ADE-203-580A
5118160B
576-w
16-bit.
ns/70
ns/80
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Untitled
Abstract: No abstract text available
Text: - PRELIMINARY - February 1996 Edition 1.0 FUJITSU P R O D U C T PR O F IL E S H E E T MB81V4405C-60/-70 CMOS 1 M X 4 BIT HYPER PAGE MODE DRAM CMOS 1,048,576 x 4 bit Hyper Page Mode Dynamic RAM The Fujitsu MB81V4405C is a fully decoded CMOS Dynamic RAM DRAM that contains 4,194,304
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MB81V4405C-60/-70
MB81V4405C
024-bits
MB81V4405C-60
MB81V4405C-70
26-LEAD
FPT-26P-M01)
F26001S-3C-3
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Untitled
Abstract: No abstract text available
Text: HM5118160BI Series 1048576-word x 16-bit Dynamic Random Access Memory HITACHI ADE-203-580A Z Rev. 1.0 May. 20, 1996 Description The Hitachi HM5118160BI is a CMOS dynamic RAM organized as 1,048,576-word x 16-bit. It employs the most advanced CMOS technology for high performance and low power. The HM5118160BI offers
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HM5118160BI
1048576-word
16-bit
ADE-203-580A
576-word
16-bit.
ns/70
ns/80
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