M48T129V
Abstract: M48T129Y
Text: M48T129Y M48T129V 5.0 or 3.3 V, 1 Mbit 128 Kbit x 8 TIMEKEEPER SRAM Features • Integrated, ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal ■ BCD coded century, year, month, day, date, hours, minutes, and seconds
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M48T129Y
M48T129V
M48T129Y:
M48T129V:
M48T129V
M48T129Y
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Untitled
Abstract: No abstract text available
Text: M68AR024D 16 Mbit 1M x16 1.8V Asynchronous SRAM OBSOLETE PRODUCT FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE: 1.65 to 1.95V I/O SUPPLY VOLTAGE: 1.5 to 1.95V 1M WORDS x 16 bits LOW POWER SRAM EQUAL CYCLE and ACCESS TIME: 70ns LOW VCC DATA RETENTION: 1.0V
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M68AR024D
TFBGA48
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AN1471
Abstract: M24XXX
Text: AN1471 Application note What happens to the M24xxx I²C EEPROM if the I²C bus communication is stopped? This Application note describes what can be attempted to set an M24xxx memory back to a known state if it has been suddenly stopped before completion of the current I²C instruction.
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AN1471
M24xxx
AN1471
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Untitled
Abstract: No abstract text available
Text: M48Z128 M48Z128Y 5.0 V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of
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M48Z128
M48Z128Y
M48Z128:
M48Z128Y:
PMDIP32
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PDF
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Untitled
Abstract: No abstract text available
Text: M68AR024D 16 Mbit 1M x16 1.8V Asynchronous SRAM OBSOLETE PRODUCT FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE: 1.65 to 1.95V I/O SUPPLY VOLTAGE: 1.5 to 1.95V 1M WORDS x 16 bits LOW POWER SRAM EQUAL CYCLE and ACCESS TIME: 70ns LOW VCC DATA RETENTION: 1.0V
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M68AR024D
TFBGA48
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M48T129Y
Abstract: STMicroelectronics
Text: M48T129Y M48T129V 5.0 or 3.3 V, 1 Mbit 128 Kbit x 8 TIMEKEEPER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal ■ BCD coded century, year, month, day, date,
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Original
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M48T129Y
M48T129V
M48T129Y:
M48T129V:
STMicroelectronics
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PDF
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Untitled
Abstract: No abstract text available
Text: M48Z128 M48Z128Y 5.0 V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of
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M48Z128
M48Z128Y
M48Z128:
M48Z128Y:
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AN1471
Abstract: ic eeprom conclusion of can bus application in automotive n
Text: AN1471 Application note What happens to the M24xxx I²C EEPROM if the I²C bus communication is stopped? This application note describes what can be attempted to set an M24xxx memory back to a known state if it has been suddenly stopped before completion of the current I²C instruction.
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AN1471
M24xxx
AN1471
ic eeprom
conclusion of can bus application in automotive n
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PDF
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Untitled
Abstract: No abstract text available
Text: M48T129Y M48T129V 5.0 or 3.3 V, 1 Mbit 128 Kbit x 8 TIMEKEEPER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal ■ BCD coded century, year, month, day, date,
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Original
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M48T129Y
M48T129V
M48T129Y:
M48T129V:
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M68AR024D
Abstract: TFBGA48
Text: M68AR024D 16 Mbit 1M x16 1.8V Asynchronous SRAM PRELIMINARY DATA FEATURES SUMMARY • SUPPLY VOLTAGE: 1.65 to 1.95V ■ I/O SUPPLY VOLTAGE: 1.5 to 1.95V ■ 1M WORDS x 16 bits LOW POWER SRAM ■ EQUAL CYCLE and ACCESS TIME: 70ns ■ ■ LOW VCC DATA RETENTION: 1.0V
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M68AR024D
TFBGA48
M68AR024D
TFBGA48
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PDF
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AN1471
Abstract: ic eeprom
Text: AN1471 APPLICATION NOTE What Happens to the M24xxx I²C EEPROM If the I²C Bus Communication is Stopped? This document describes what can be attempted to set an M24xxx device back to a known state if it has been suddenly stopped before completion of the current I²C instruction, for example due to a power failure
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AN1471
M24xxx
AN1471
ic eeprom
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M48Z128
Abstract: M48Z128V M48Z128Y AN1012
Text: M48Z128 M48Z128Y, M48Z128V 5.0 V or 3.3 V, 1 Mbit 128 Kbit x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of
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Original
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M48Z128
M48Z128Y,
M48Z128V
M48Z128:
M48Z128Y:
M48Z128V:
PMDIP32
M48Z128
M48Z128V
M48Z128Y
AN1012
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Untitled
Abstract: No abstract text available
Text: TH I S DRAW I NG IS UNPUBLI S HE D. RELEASED BY C O P Y RI G HT 20 TYCO ELECTRONICS F OR CORPORATION. ALL PUBLICATION R 1G H T S 20 L OC RESERVED. D I ST PT R E V LTR I S I O N S DESCRIPTION DATE DWN APVD RELEASED R E V I S E D PER 0 G 3 B - 0 I 19- 01 12NOV2Û Û I
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12NOV2Û
94-VO,
NOV20
07NOV2001
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PDF
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Untitled
Abstract: No abstract text available
Text: TH I S DRAW ING IS UNPUBLI SHED. C O P Y R I G HT 2 0 RELEASED BY TYCO ELECTRONICS FOR CORPORATION. ALL PUBLICATION R 1G H T S 20 LOC PT RESERVED. REV I S IONS D I ST LTR DESCRIPTION DATE DWN APVD RELEASED REVISED PER 0 G 3 B - 0 I 19-01 12 N O V 2 Û Û I
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NOV20
07NOV2001
S-282893
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