DSA0066810.pdf by Cypress Semiconductor

Partial File Text CY7C1312BV18 CY7C1314BV18 18 Mbit QDR® II SRAM Two Word Burst Architecture Features Functional Description Separate independent read and write data ports Supports concurrent transact
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CY7C1312 CY7C1312BV18 CY7C1314BV18

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