DSASW00419458.pdf by Xilinx

Partial File Text Application Note: Spartan-6 FPGAs Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s) XAPP1064 (v1.1) June 3, 2010 Author: NIck Sawyer Summary Spartan®-6 devices conta
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"parameters S" BUFIO2 clock_generator_ddr_s8_diff Deserialization iodelay ISERDES ISERDES spartan 6 ISERDES2 OSERDES oserdes2 oserdes2 DDR spartan6 serdes SP601 vhdl code for phase frequency detector vhdl code for phase frequency detector for FPGA video pattern generator using vhdl X10640 XAPP1064