OSERDES
Abstract: oserdes2 DDR spartan6 XAPP1064 ISERDES2 oserdes2 serdes clock_generator_ddr_s8_diff ISERDES spartan 6 SP601 Clock-Generator
Text: Application Note: Spartan-6 FPGAs Source-Synchronous Serialization and Deserialization up to 1050 Mb/s XAPP1064 (v1.0) December 23, 2009 Author: NIck Sawyer Summary Spartan -6 devices contain input SerDes (ISERDES) and output SerDes (OSERDES) blocks. These primitives simplify the design of serializing and deserializing circuits, while allowing
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XAPP1064
OSERDES
oserdes2 DDR spartan6
XAPP1064
ISERDES2
oserdes2
serdes
clock_generator_ddr_s8_diff
ISERDES spartan 6
SP601
Clock-Generator
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transistor s3050
Abstract: S3050 R488 TRANSISTOR SUBSTITUTION DATA BOOK capacitor stream resistor 220 TRANSISTOR MMBT3904LT1 S3052 S3057 SDM7128-XC
Text: Part Number S3057/S3050/S3052 Revision 2.01 - March 26, 2001 Multi-Rate Application Note PRELIMINARY APPLICATION NOTE S3057 Xcvr, S3050 CRU, S3052 PM, and Sumitomo SDM7128-XC Optic Xcvr. INTRODUCTION The AMCC S3057 transceiver chip is a fully integrated serialization/deserialization SONET STS-48/OC-48
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S3057/S3050/S3052
S3057
S3050
S3052
SDM7128-XC
STS-48/OC-48
STS-24/OC-24
STS-12/OC-12
transistor s3050
R488
TRANSISTOR SUBSTITUTION DATA BOOK
capacitor stream
resistor 220
TRANSISTOR MMBT3904LT1
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SCM7102-XC
Abstract: S1201 S1202 S3019 SDM7101-XC SDM7102-XC transistor 2n3904
Text: Revision 1.0 - November 22, 2000 APPLICATION NOTE S3019 with 1 x 9 Sumitomo 5 V Fiber Optics and S1202 NILE/S1201 CONGO Introduction The AMCC S3019 SONET/SDH transceiver and clock recovery chip is a fully integrated serialization/deserialization SONET STS-12/STM-4 622.08 Mbps and STS-3/STM-1 (155.52 Mbps) interface device. This device is
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S3019
S1202
NILE/S1201
STS-12/STM-4
STS-12/STS-4
D193/R317
SCM7102-XC
S1201
SDM7101-XC
SDM7102-XC
transistor 2n3904
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UCF example for QFP
Abstract: RX 3E CLKFX180 vhdl 4-bit binary calculator SPARTAN-3E FT256 PQ208 TQ144 VQ100 XAPP485
Text: Application Note: Spartan-3E FPGA Family 1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666 Mbps R XAPP485 v1.1 November 10, 2006 Author: Nick Sawyer Summary Spartan -3E devices are used in a wide variety of applications requiring 1:7 deserialization at
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XAPP485
UCF example for QFP
RX 3E
CLKFX180
vhdl 4-bit binary calculator
SPARTAN-3E
FT256
PQ208
TQ144
VQ100
XAPP485
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Untitled
Abstract: No abstract text available
Text: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.
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21-Bit
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222
MAX9209/MAX9211/MAX9213/
MAX9215
MAX9210/MAX9212/MAX9214/MAX9216
D222EUM
MAX9220EUM
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TRANSISTOR SUBSTITUTION DATA BOOK
Abstract: s3067 OC-24 S3062 S3078 STS-48 Signal Path Designer
Text: Part Number S3078, S3067, S3062 Revision 2.01 - March 26, 2001 Multi-Rate APPLICATION NOTE S3078 CRU, S3067 Xcvr, S3062 PM w/FEC and Sumitomo Fiber Optic Xcvr. INTRODUCTION The AMCC S3067 transceiver chip is a fully integrated serialization/deserialization SONET STS-48/OC-48, STS-24/
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S3078,
S3067,
S3062
S3078
S3067
S3062
STS-48/OC-48,
STS-24/
OC-24,
TRANSISTOR SUBSTITUTION DATA BOOK
OC-24
STS-48
Signal Path Designer
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BLM11B601S
Abstract: blm11b601 BLM11B601SPB BLM31b601s BLM31B601SPB S3033
Text: Part Number S3033 Revision 1.0 - March 14, 2001 S3033 APPLICATION NOTE Board Decoupling Guidelines SONET/SDH/ATM OC-3/12 Transceiver S3033 Example The S3033 transceiver chip is a fully integrated serialization/deserialization SONET OC-12 622.08 Mbit/s and
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S3033
OC-3/12
S3033
OC-12
BLM31B601SPB
BLM11B601SPB
D274/R483
BLM11B601S
blm11b601
BLM11B601SPB
BLM31b601s
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optical-transceiver surface mount
Abstract: S1201 S1202 S3019 SCM7101-XC SCM7102-XC
Text: Revision 1.0 - December 1, 2000 APPLICATION NOTE S3019 with 1 x 9 Sumitomo Fiber Optics and S1202 NILE/S1201 CONGO Introduction The AMCC S3019 SONET/SDH transceiver and clock recovery chip is a fully integrated serialization/deserialization SONET STS-12/STM-4 622.08 Mbps and STS-3/STM-1 (155.52 Mbps) interface device. This device is
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S3019
S1202
NILE/S1201
STS-12/STM-4
STS-12/STM-4
D192/R316
optical-transceiver surface mount
S1201
SCM7101-XC
SCM7102-XC
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DS90CR216A
Abstract: DS90CR218A MAX9210 MAX9215 MAX9222
Text: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.
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21-Bit
MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222
MAX9209/MAX9211/MAX9213/
MAX9215
MAX9210/MAX9212/MAX9214/MAX9216
DS90CR216A
DS90CR218A
MAX9210
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simple block diagram for digital clock
Abstract: simple diagram for digital clock XAPP265 digital clock diagram digital clock vhdl code VHDL of 4-BIT LEFT SHIFT REGISTER X0Y24 digital clock notes signal path designer digital clock verilog code
Text: Application Note: Virtex-II Family R XAPP265 1.1 November 7, 2001 Summary High-Speed Data Serialization and Deserialization (840 Mb/s LVDS) Author: Nick Sawyer The serial transfer of data between cards on a backplane is often a requirement in digital system design. Serializing the data makes greater use of the available resources (pins). A
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XAPP265
64-bit
simple block diagram for digital clock
simple diagram for digital clock
XAPP265
digital clock diagram
digital clock vhdl code
VHDL of 4-BIT LEFT SHIFT REGISTER
X0Y24
digital clock notes
signal path designer
digital clock verilog code
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Untitled
Abstract: No abstract text available
Text: SN65LVDS152 MuxIt RECEIVER-DESERIALIZER SLLS445 – DECEMBER 2000 D A Member of the MuxItt Serializer- SN65LVDS152DA Marked as 65LVDS152 (TOP VIEW) Deserializer Building-Block Chip Family D Supports Deserialization of One Serial Link D D D D D D D Data Channel Input at Rates up to
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SN65LVDS152
SLLS445
TIA/EIA-644-A
32-Pin
5LVDS152DA
SN65LVDS152DAR
SLLC055,
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SCM7102-XC
Abstract: S1202 S3037 SCM7101-XC
Text: S3037 WITH 1 X 9 SUMITOMO 3.3V FIBER OPTICS APPLICATION NOTE S3037 WITH 1 X 9 SUMITOMO 3.3V FIBER OPTICS APPLICATION NOTE S3037 S3037 INTRODUCTION The AMCC S3037 SONET/SDH transceiver and clock recovery chip is a fully integrated serialization/ deserialization SONET STS-12/STM-4 622.08 Mbps and STS-3/STM-1 (155.52 Mbps) interface device. This
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S3037
S3037
STS-12/STM-4
STS-12/STM-4
SCM7102-XC
S1202
SCM7101-XC
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S3056
Abstract: S3057 SDM7128-XC STS-48 S3052 Signal Path Designer
Text: Part Number S3057 Revision 1.0 - April 26, 2000 PRELIMINARY APPLICATION NOTE S3057 Transceiver, S3056 CRU, S3052 Performance Monitor, Sumitomo SDM7128-XC Optic Transciever INTRODUCTION The AMCC S3057 transceiver chip is a fully integrated serialization/deserialization SONET STS-48/OC-48 2.488
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S3057
S3057
S3056
S3052
SDM7128-XC
STS-48/OC-48
STS-24/OC-24
STS-12/OC-12
STS-48
S3052
Signal Path Designer
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2N3904 PNP
Abstract: S1202 S3037 SDM7101-XC SDM7102-XC
Text: S3037, S1202 NILE, AND SUMITOMO 5 V FIBER OPTIC XCVR APPLICATION NOTE S3037, S1202 NILE, AND SUMITOMO 5 V FIBER OPTIC XCVR APPLICATION NOTE INTRODUCTION The AMCC S3037 SONET/SDH transceiver and clock recovery chip is a fully integrated serialization/ deserialization SONET STS-12/STM-4 622.08 Mbps and STS-3/STM-1 (155.52 Mbps) interface device. This
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S3037,
S1202
S3037
STS-12/STM-4
STS-12/STS-4
2N3904 PNP
SDM7101-XC
SDM7102-XC
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S1201
Abstract: S1202 S3019 SDM7101-XC SDM7102-XC
Text: Part Number S3019 February 9, 2000 / Revision 1.0 S3019 with 1 x 9 Sumitomo 5 V Fiber Optics and S1202 NILE/S1201 CONGO APPLICATION NOTE Introduction The AMCC S3019 SONET/SDH transceiver and clock recovery chip is a fully integrated serialization/deserialization SONET STS-12/STM-4 622.08 Mbps and STS-3/STM-1 (155.52 Mbps) interface device. This device is
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S3019
S3019
S1202
NILE/S1201
STS-12/STM-4
STS-12/STS-4
S1201
SDM7101-XC
SDM7102-XC
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BLM11B601S
Abstract: BLM11B601SPB BLM31B601SPB S3033
Text: Part Number S3033 Revision 1.0 - January 20, 2000 S3033 APPLICATION NOTE Board Decoupling Guidelines SONET/SDH/ATM OC-3/12 Transceiver S3033 Example The S3033 transceiver chip is a fully integrated serialization/deserialization SONET OC-12 622.08 Mbit/s and
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S3033
OC-3/12
S3033
OC-12
BLM31B601SPB
BLM11B601SPB
BLM11B601S
BLM11B601SPB
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SMPTE checkfield pattern
Abstract: HOTLink WFM700M SDI pattern generator WFM700 smpte rp 198 hd-SDI driver CYP15G0404DX EG-34 CYP15G0404DXB
Text: HD-SDI and SD-SDI SMPTE Jitter Performance of the Independent Channel HOTLinkII Transceiver in a System AN5004 Introduction The HOTLink II™ family of physical layer PHY devices is a point-to-point or point-to-multipoint communications building block that provides serialization, deserialization, optional
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AN5004
8B/10B
SMPTE checkfield pattern
HOTLink
WFM700M
SDI pattern generator
WFM700
smpte rp 198
hd-SDI driver
CYP15G0404DX
EG-34
CYP15G0404DXB
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SMPTE checkfield pattern
Abstract: smpte rp 198 SDI scrambler RP-178 HD-SDI deserializer 16 bit parallel EG-34 HD-SDI serializer 16 bit parallel smpte 274m 198-1998 CYV15G0101DXB
Text: SD-SDI and HD-SDI Checkfield Testing on HOTLink II Transceivers for SMPTE Pathological Conditions AN084 Introduction The HOTLink II™ family of physical layer PHY devices is a point-to-point or point-to-multipoint communications building block that provides serialization, deserialization, optional
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AN084
8B/10B
SMPTE checkfield pattern
smpte rp 198
SDI scrambler
RP-178
HD-SDI deserializer 16 bit parallel
EG-34
HD-SDI serializer 16 bit parallel
smpte 274m
198-1998
CYV15G0101DXB
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XCF02SV020C
Abstract: Xilinx xcf02sv020c manual SMHU diode c329 JP105 xcf02sv020 C337 W 63 c338 pin details SMHU transistor c331
Text: High Speed Deserialization Board HSDB HSC-ADC-FPGA FEATURES FUNCTIONAL BLOCK DIAGRAM STANDARD USB 2.0 SERIAL LVDS HIGH SPEED ADC EVALUATION BOARD PS HSC-ADC-FPGA PS REG n FILTERED ANALOG INPUT Any high speed ADC evaluation board that supports serial LVDS digital output format
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XC2V250
133MHz
120-PIN
05053-0RL
XC2V250-5FG256C
XCF02SV020C
CBSB-14-01A-RT
SNT-100-BK-G-H
HSC-ADC-FPGA-9289
XCF02SV020C
Xilinx xcf02sv020c
manual SMHU
diode c329
JP105
xcf02sv020
C337 W 63
c338 pin details
SMHU
transistor c331
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2N3904 PNP
Abstract: 470 resistor S1202 S3037 V23806-A84-C2 V23826-H18-C63
Text: S3037 WITH 1 X 9 INFINEON FIBER OPTICS APPLICATION NOTE S3037 WITH 1 X 9 INFINEON FIBER OPTICS APPLICATION NOTE S3037 INTRODUCTION The AMCC S3037 SONET/SDH transceiver and clock recovery chip is a fully integrated serialization/ deserialization SONET STS-12/STM-4 622.08 Mbps and STS-3/STM-1 (155.52 Mbps) interface device. This
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S3037
S3037
STS-12/STM-4
STS-12/STM-4
D201/R325
2N3904 PNP
470 resistor
S1202
V23806-A84-C2
V23826-H18-C63
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ANSI/TIA/EIA-644
Abstract: MAX9232 MAX9232EUM
Text: XX-XXXX; Rev 0; 9/05 Programmable Spread-Spectrum and DC-Balance 21-Bit Deserializer Features The MAX9232 deserializes three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A separate parallel-rate LVDS clock provides the timing for deserialization. The MAX9232 features spread-spectrum capability, allowing the output data and clock
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21-Bit
MAX9232
32kHz
33MHz
MAX9232EUM
MAX9232
ANSI/TIA/EIA-644
MAX9232EUM
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G958
Abstract: M69899VP STM-16 M6989
Text: MITSUBISHI SEMICONDUCTOR <SOI/CMOS> Preliminary M69899VP 1:16 2.488 Gbps Demultiplexer [with Differential Outputs] DESCRIPTION The M69899VP demultiplexer chip is an integrated deserialization SONET OC-48 2.488 Gbps interface device. The chip performs serial-to-parallel functions in conformance with SONET/SDH transmission standards. The
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M69899VP
M69899VP
OC-48
64-pin
PDOP13
PDON13
PDOP14
PDON14
PDOP15
PDON15
G958
STM-16
M6989
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S3155
Abstract: SDH -209 SDH ADM S4802
Text: S3155 Serial OC-48 - to - 16bit Transceiver P RODUCT BR IE F The S3155 SONET/SDH transceiver chip is a fully integrated serialization/deserialization SONET OC-48 2.488 Gbps–2.67 Gbps interface device. The S3155 receives an OC-48 scrambled Non-Return-to-Zero (NRZ) signal and recovers the
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S3155
OC-48
16bit
S3155
OC-48
SDH -209
SDH ADM
S4802
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M6989
Abstract: G958 M69899VP STM-16
Text: MITSUBISHI SEMICONDUCTOR <SOI/CMOS> Preliminary M69899VP 1:16 2.488 Gbps Demultiplexer [with Differential Outputs] DESCRIPTION The M69899VP demultiplexer chip is an integrated deserialization SONET OC-48 2.488 Gbps interface device. The chip performs serial-to-parallel functions in conformance with SONET/SDH transmission standards. The
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M69899VP
M69899VP
OC-48
64-pin
PD0P13
PDON13
PD0P14
P00N14
PD0P15
PD0N15
M6989
G958
STM-16
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