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    XRT71D00 Search Results

    XRT71D00 Datasheets (8)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    XRT71D00 Exar E3-DS3-STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER Original PDF
    XRT71D00 Exar E3/DS3/STS-1 JITTER ATTENUATOR Original PDF
    XRT71D00ID Exar DS3/E3 JITTER ATTENUATOR IC Original PDF
    XRT71D00IQ Exar DS3/E3 JITTER ATTENUATOR IC Original PDF
    XRT71D00IQ Exar E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER Original PDF
    XRT71D00IQ32 Exar DS3/E3 JITTER ATTENUATOR IC Original PDF
    XRT71D00IQ-F Exar Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers, Integrated Circuits (ICs), IC JITTER ATTENUATOR SGL 32TQFP Original PDF
    XRT71D00IQTR-F Exar Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers, Integrated Circuits (ICs), IC JITTER ATTENUATOR SGL 32TQFP Original PDF

    XRT71D00 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CR14

    Abstract: XRT71D00 XRT73L00 XRT73L02 Jaro Components
    Text: TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 DESIGNING THE XRT71D00 AND THE XRT73L00 DEVICES TO OPERATE IN THE HOST MODE, AND TO


    Original     		PDF TAN-042 XRT71D00 XRT73L00 XRT73L00 CR14 XRT73L02 Jaro Components

    850C

    Abstract: GR-253 GR-499-CORE TBR24 XRT71D00 XRT71D00IQ 58438 31314
    Text:  XRT71D00 E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER JULY 2000 REV. 1.01 GENERAL DESCRIPTION The XRT71D00 is a single channel, single chip Jitter Attenuator, that meets the Jitter requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR253 standards.


    Original     		PDF XRT71D00 XRT71D00 TBR-24, GR-499 GR253 GR-253 TBR24 850C GR-499-CORE TBR24 XRT71D00IQ 58438 31314

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET Communications T3/STS-1/E3 XRT71D00 Single-Chip Jitter Attenuator for High-Speed DS3/E3 WANs Features • Accepts "jittery" clock and data from an LIU IC • Internally reduces clock and data signal jitter • Outputs "smooth" data to the terminal equipment


    Original     		PDF XRT71D00 32-bits 24-pin 32-pin TBR-24 34Mbits/s TBR-24, GR499CORE

    CR14

    Abstract: XRT71D00 XRT73L00 XRT73L02
    Text: TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary September 1, 2001 Revision 1.04 DESIGNING THE XRT71D00 AND THE XRT73L00 DEVICES TO OPERATE IN THE HOST MODE, AND TO


    Original     		PDF TAN-042 XRT71D00 XRT73L00 XRT73L00 CR14 XRT73L02

    CR14

    Abstract: XRT71D00 XRT73L00 XRT73L02 GRM43 X7R Jaro
    Text: TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary October 19, 2001 Revision 1.05 DESIGNING THE XRT71D00 AND THE XRT73L00 DEVICES TO OPERATE IN THE HOST MODE, AND TO


    Original     		PDF TAN-042 XRT71D00 XRT73L00 XRT73L00 CR14 XRT73L02 GRM43 X7R Jaro

    role of microprocessor

    Abstract: DS3 multiplex demultiplex 850C CR21 GR-499-CORE TBR24 XRT71D00 XRT7300 E3 multiplex demultiplex
    Text: áç XRT71D00 PRELIMINARY DS3/E3 JITTER ATTENUATOR IC FEBRUARY 2000 REV. P1.0.0 GENERAL DESCRIPTION • Selectable buffer size of 16 and 32 bits The XRT71D00 is a single chip IC which accepts “jittery” clock and data signals from a LIU, internally reduces and smooths the clock and data jitter, then ouputs the smoothed data to the Terminal Equipment.


    Original     		PDF XRT71D00 XRT71D00 TBR24 34Mbit/s role of microprocessor DS3 multiplex demultiplex 850C CR21 GR-499-CORE XRT7300 E3 multiplex demultiplex

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET Communications APPNOTE TAN-042 XRT71D00 Single-Chip Jitter Attenuator for High-Speed DS3/E3 WANs Features • Accepts "jittery" clock and data from an LIU IC • Internally reduces clock and data signal jitter • Outputs "smooth" data to the terminal equipment


    Original     		PDF TAN-042 XRT71D00 32-bits 24-pin 32-pin TBR-24 34Mbits/s TBR-24,

    Untitled

    Abstract: No abstract text available
    Text: áç XRT71D00 E3/DS3/STS-1 JITTER ATTENUATOR SEPTEMBER 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT71D00 is a single channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristic requirements specified in the ETSI TBR-24, Bellcore GR-499-CORE and GR-253-CORE standards.


    Original     		PDF XRT71D00 XRT71D00 TBR-24, GR-499-CORE GR-253-CORE GR499-CORE

    CR14

    Abstract: XRT71D00 XRT73L00 XRT73L02
    Text: TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary June 7, 2001 Revision 1.02 DESIGNING THE XRT71D00 AND THE XRT73L00 DEVICES TO OPERATE IN THE HOST MODE, AND TO


    Original     		PDF TAN-042 XRT71D00 XRT73L00 XRT73L00 CR14 XRT73L02

    XRT73L02

    Abstract: CR14 XRT71D00 XRT73L00 Jaro Components
    Text: TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary May 23, 2001 Revision 1.01 DESIGNING THE XRT71D00 AND THE XRT73L00 DEVICES TO OPERATE IN THE HOST MODE, AND TO


    Original     		PDF TAN-042 XRT71D00 XRT73L00 XRT73L00 XRT73L02 CR14 Jaro Components

    850C

    Abstract: GR-253-CORE GR-499-CORE TBR24 XRT71D00 XRT71D00IQ PLL IC 566 2609 al
    Text: áç XRT71D00 E3/DS3/STS-1 JITTER ATTENUATOR SEPTEMBER 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT71D00 is a single channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristic requirements specified in the ETSI TBR-24, Bellcore GR-499-CORE and GR-253-CORE standards.


    Original     		PDF XRT71D00 XRT71D00 TBR-24, GR-499-CORE GR-253-CORE TBR24 GR-253CORE 850C TBR24 XRT71D00IQ PLL IC 566 2609 al

    GR-499-CORE

    Abstract: XRT71D00 XRT7300 GR 917 ANT-20
    Text: TAN-048 Ap Note – How the Jitter Transfer Characteristics of the XRT71D00 DS3/E3/STS-1 Jitter Attenuator IC compares with the Jitter Transfer Characteristic requirements of Bellcore GR-499-CORE March 20, 2001 TAN-048 – AP NOTE – HOW THE JITTER TRANSFER


    Original     		PDF TAN-048 XRT71D00 GR-499-CORE GR-499CORE GR-499-CORE XRT7300 GR 917 ANT-20

    CR21

    Abstract: GR-499-CORE TBR24 XRT71D00 XRT7300 XRT7302 XRT73L03 role of microprocessor
    Text:  XRT71D00 PRELIMINARY DS3/E3 JITTER ATTENUATOR IC OCTOBER 1999 REV. 1.0.6 FEATURES • Meets output jitter generation requirement as spec- ified by ETSI TBR24 • A single-chip that does the following: • Accepts “jittery” clock and data from an LIU IC


    Original     		PDF XRT71D00 TBR24 TBR24 34Mbit/s XRT71D00ID XRT71D00IQ32 CR21 GR-499-CORE XRT71D00 XRT7300 XRT7302 XRT73L03 role of microprocessor

    EXAR XR2209

    Abstract: XR16C2850 XR68C681 XR88C192 ST16C650A
    Text: ABOUT EXAR I PRODUCTS I INDEX I SALES INFO I INFORMATION REQUEST I SEARCH I HELP I Exar Products Alphanumeric Index To access product information and data sheets, click on the part number below. ST16C1450 ST16C1451 ST16C1550 ST16C1551 ST16C2450 ST16C2550 ST16C2552


    Original     		PDF ST16C1450 ST16C1451 ST16C1550 ST16C1551 ST16C2450 ST16C2550 ST16C2552 ST16C450 ST16C452-PS ST16C454 EXAR XR2209 XR16C2850 XR68C681 XR88C192 ST16C650A

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET Communications DS3/E3 Jitter Attenuator XRT71D03 Three Channel DS3/E3/STS-1 Jitter Attenuator, STS-1 to DS3 Desynchronizer Features • Supports DS3/E3/STS-1 rates • Each channel can operate at different data rates • Selectable buffer size 16- or 32-bit


    Original     		PDF XRT71D03 32-bit) 64-pin XRT71D03) 80-pin XRT71D04) XRT71D00, XRT71D03, XRT71D04 TBR-24

    NAIS 210 RELAY

    Abstract: ic 393 k 4213 0X13 DS3-M13 XRT72L52
    Text: áç XRT72L52 PRELIMINARY TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.2 GENERAL DESCRIPTION The XRT72L52, 2 Channel DS3/E3 Framer IC is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bitfields within an “outbound” DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an “inbound” DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the “User Data”.


    Original     		PDF XRT72L52 XRT72L52, XRT72L52 DS3-M13, NAIS 210 RELAY ic 393 k 4213 0X13 DS3-M13

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET Communications XRT71D04 DS3/E3 Jitter Attenuator Features • Supports DS3/E3/STS-1 rates • Each channel can operate at different data rates • Selectable buffer size 16- or 32-bit • Available in either a 64-pin (XRT71D03), or a 80-pin (XRT71D04) TQFP package


    Original     		PDF XRT71D04 32-bit) 64-pin XRT71D03) 80-pin XRT71D04) XRT71D00, XRT71D03 TBR-24

    Untitled

    Abstract: No abstract text available
    Text: I ABOUT EXAR I PRODUCTS I INDEX I SALES INFORMATION I INFORMATION REQUEST I SEARCH I HELP I DS3/E3 Product Selector Guide DS3/E3 Products DS3/E3 Line Interfaces Part No. #of Channels Data Rates Clock Recovery Temp Range Operating Power Supply Max Current Package s


    Original     		PDF 111mA 106mA 133mA XRT7295 XRT7295E XRT7296 XRT7298 XRT7300 XRT73L00

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET Communications XRT75L00 Single-Chip Line Interface Unit LIU With Jitter Attenuator (JA) for DS3/E3 Environments Features: Receiver: • On-Chip Clock and Data Recovery Circuit for High-Input Jitter Tolerance • On-Chip B3ZS/HDB3 Encoder/Decoder Can be Disabled or Enabled


    Original     		PDF XRT75L00 XRT75L00D GR-499 GR-253 TBR-24,

    6 PORT LIU

    Abstract: XRT75VL00 QUICC Engine MC68360 XRT7300 XRT73L00A XRT73L02M XRT73L03A XRT73L03B XRT73L04A
    Text: TAN-025 Interfacing the Microprocessor Serial Interface of the XRT730X/XRT75L0X Family of DS3/E3/STS-1 LIU Devices to the SPI Port of the MC68360 QUICC Device Rev 1.3 July 16, 2004 Interfacing the Microprocessor Serial Interface of the XRT730X/XRT750X Family of DS3/E3/STS-1 LIU Devices to the SPI


    Original     		PDF TAN-025 XRT730X/XRT75L0X MC68360 XRT730X/XRT750X XRT7300 XRT73L00A XRT73L02M XRT73L03A 6 PORT LIU XRT75VL00 QUICC Engine XRT7300 XRT73L00A XRT73L02M XRT73L03A XRT73L03B XRT73L04A

    T7100

    Abstract: C157 TANT01 ICT R7 HCT244 P300 XRT71D00 XRT7300 P30012 BG1A
    Text: A B C D +3.3V GND +5V DB25 P8 P3 P1 P2 1 1 1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 + 500 R11 R7 + X6 X5 X4 5 5 0.1uF C13 3.9V ZDIODE D5 0.1uF C7 0.1uF C2 0.1uF C3 VDD HOST MODE RESET SWITCH RESET SWSPDT R14 22K SMDRC VDD 5 4 2 3


    Original     		PDF HCT244 T71D00 RT71D00 T7100 C157 TANT01 ICT R7 HCT244 P300 XRT71D00 XRT7300 P30012 BG1A

    IN134

    Abstract: ic 393 datasheet relay NAIS 5v 5 pin 74hct00 dmo 365 r NAIS 210 RELAY NAIS Relay 5v t90 series 0X13 DS3-M13
    Text: áç XRT72L52 PRELIMINARY TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER JANUARY 2001 REV. P1.1.3 GENERAL DESCRIPTION The XRT72L52, 2 Channel DS3/E3 Framer IC is designed to accept “User Data” from the Terminal Equipment and insert this data into the “payload” bitfields within an “outbound” DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an “inbound” DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the “User Data”.


    Original     		PDF XRT72L52 XRT72L52, XRT72L52 DS3-M13, IN134 ic 393 datasheet relay NAIS 5v 5 pin 74hct00 dmo 365 r NAIS 210 RELAY NAIS Relay 5v t90 series 0X13 DS3-M13

    xr82c684

    Abstract: XRT75L00D XR16C2850 XR16L2750 XR68C681 XR88C192 ST16C650A
    Text: ABOUT EXAR I PRODUCTS I INDEX I SALES INFO I INFORMATION REQUEST I SEARCH I HELP I Exar Products Alphanumeric Index To access product information and data sheets, click on the part number below. ST16C1450 ST16C1451 ST16C1550 ST16C1551 ST16C2450 ST16C2550 ST16C2552


    Original     		PDF ST16C1450 ST16C1451 ST16C1550 ST16C1551 ST16C2450 ST16C2550 ST16C2552 ST16C450 ST16C452-PS ST16C454 xr82c684 XRT75L00D XR16C2850 XR16L2750 XR68C681 XR88C192 ST16C650A

    ANSI T1.105.03B 1997

    Abstract: No abstract text available
    Text: DATA SHEET Communications XRT71D03 DS3/E3 Jitter Attenuator Features • Supports DS3/E3/STS-1 rates • Each channel can operate at different data rates • Selectable buffer size 16- or 32-bit • Available in either a 64-pin (XRT71D03), or a 80-pin (XRT71D04) TQFP package


    Original     		PDF XRT71D03 32-bit) 64-pin XRT71D03) 80-pin XRT71D04) XRT71D00, XRT71D03, XRT71D04 TBR-24 ANSI T1.105.03B 1997