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    XC9510 Price and Stock

    AMD XC95108-15PC84C

    IC CPLD 108MC 15NS 84PLCC
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    AMD XC95108-7TQ100I

    IC CPLD 108MC 7.5NS 100TQFP
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    AMD XC95108-7PQ160C

    IC CPLD 108MC 7.5NS 160QFP
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    AMD XC95108-15PQ160I

    IC CPLD 108MC 15NS 160QFP
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    AMD XC95108-10TQ100I

    IC CPLD 108MC 10NS 100TQFP
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    XC9510 Datasheets (196)

    Part ECAD Model Manufacturer Description Curated Type PDF
    XC9510 Torex Semiconductor Synchronous Step-Down DC/DC Converter With Built-In LDO Regulator Plus Voltage Detector Original PDF
    XC9510 Torex Semiconductor Synchronous Step-Down DC/DC Converter with Built-In LDO Regulator In Series plus Voltage Detector Original PDF
    XC95103SL Torex Semiconductor Synchronous Step-Down DC/DC Converter with Built-In LDO Regulator In Series plus Voltage Detector Original PDF
    XC95103SR Torex Semiconductor Synchronous Step-Down DC/DC Converter with Built-In LDO Regulator In Series plus Voltage Detector Original PDF
    XC95106SL Torex Semiconductor Synchronous Step-Down DC/DC Converter with Built-In LDO Regulator In Series plus Voltage Detector Original PDF
    XC95106SR Torex Semiconductor Synchronous Step-Down DC/DC Converter with Built-In LDO Regulator In Series plus Voltage Detector Original PDF
    XC95108 Unknown XC95108 In-System Programmable CPLD Original PDF
    XC95108 Xilinx In-System Programmable CPLD Family Original PDF
    XC95108 Xilinx The Programmable Logic Data Book Original PDF
    XC95108-10PC84C Xilinx In-System Programmable CPLD Original PDF
    XC95108-10PC84C Xilinx XC95108-10PC84C - NOT RECOMMENDED for NEW DESIGN Original PDF
    XC95108-10PC84C Xilinx In-System Programmable CPLD Original PDF
    XC95108-10PC84C Xilinx In-System Programmable CPLD Original PDF
    XC95108-10PC84C Xilinx Over 600 obsolete distributor catalogs now available on the Datasheet Archive - CMOS CPLD, 108 Macrocells, 6 Func Blks, 108 Regs, 10ns, Pkg Style 84 Lead PLCC Scan PDF
    XC95108-10PC84I Xilinx In-System Programmable CPLD Original PDF
    XC95108-10PC84I Xilinx In-System Programmable CPLD Original PDF
    XC95108-10PC84I Xilinx 108 MACROCELL 5 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN Original PDF
    XC95108-10PC84I Xilinx In-System Programmable CPLD Original PDF
    XC95108-10PCG84C Xilinx XC95108-10PCG84C Original PDF
    XC95108-10PCG84I Xilinx XC95108-10PCG84I - NOT RECOMMENDED for NEW DESIGN Original PDF
    ...

    XC9510 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    XC9500

    Abstract: XC95108 GSR 10,8
    Text: 1 XC95108 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2400 usable gates Up to 108 user I/O pins


    Original     		PDF XC95108 36V18 84-Pin 100-Pin 160-Pin XC95108 PQ100 TQ100 PQ160 XC9500 GSR 10,8

    XC95108

    Abstract: XC95108-10PQ160C xc95108-10pqg100i XC95108-20PQG160I TQG100 XC95108-15PC84C PGC84 XC95108-20PQ100I
    Text: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – XC95108 In-System Programmable CPLD R DS066 v5.0 May 17, 2013 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates


    Original     		PDF XC95108 DS066 36V18 PQ160 XCN11010 XC95108-10PQ160C xc95108-10pqg100i XC95108-20PQG160I TQG100 XC95108-15PC84C PGC84 XC95108-20PQ100I

    XC9510E

    Abstract: CDRH4D28C CDRH5D28 CDRH6D28 CDRH6D38 XC9510 step down Voltage Regulator sop8 XC9510b
    Text: XC9510 Series ETR1007_001 Synchronous Step-Down DC/DC Converter with Built-In LDO Regulator In Series Plus Voltage Detector •GENERAL DESCRIPTION The XC9510 series consists of a step-down DC/DC converter and a high-speed LDO regulator connected in series with the


    Original     		PDF XC9510 ETR1007 800mA XC9510E CDRH4D28C CDRH5D28 CDRH6D28 CDRH6D38 step down Voltage Regulator sop8 XC9510b

    XC9500

    Abstract: XC95108
    Text:  XC95108 In-System Programmable CPLD March, 1997 Version 1.1 Product Specification Features Power Management • 7.5 ns pin-to-pin logic delays on all pins • fCNT to 125 MHz • 108 macrocells with 2400 usable gates • Up to 108 user I/O pins • 5 V in-system programmable (ISP)


    Original     		PDF XC95108 36V18 84-Pin 100-Pin 160-Pin XC95108 XC95108F PQ100 TQ100 XC9500

    XC95108

    Abstract: XC95108-10PQ160C XC9510815PQ10 XC95108-7TQ100C
    Text: XC95108 In-System Programmable CPLD R DS066 v4.3 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates Up to 108 user I/O pins 5V in-system programmable


    Original     		PDF XC95108 DS066 36V18 XC9500 PQ160 XC95108-10PQ160C XC9510815PQ10 XC95108-7TQ100C

    PC84

    Abstract: XC95108 PC84 84-Pin Plastic Leaded Chip Carrier PLCC
    Text:  XC95108 In-System Programmable CPLD June 1, 1996 Version 1.0 Preliminary Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC95108 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize


    Original     		PDF XC95108 36V18 84-Pin PQ100 100-Pin TQ100 PQ160 PC84 PC84 84-Pin Plastic Leaded Chip Carrier PLCC

    PC84 84-Pin Plastic Leaded Chip Carrier

    Abstract: XC95108 XC95108-15PC84C XC95108-15TQ100I XC95108-20TQ100I PC84 XC9500 XC95108-20TQ100C XC95108-7TQ100C
    Text: XC95108 In-System Programmable CPLD R DS066 v4.3 March 1, 2004 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates Up to 108 user I/O pins 5V in-system programmable


    Original     		PDF XC95108 DS066 36V18 XC9500 PQ160 PC84 84-Pin Plastic Leaded Chip Carrier XC95108-15PC84C XC95108-15TQ100I XC95108-20TQ100I PC84 XC95108-20TQ100C XC95108-7TQ100C

    CDRH4D28C

    Abstract: XC9510
    Text: October 28, 2003 Ver. 4 XC9510 Series Synchronous Step-Down DC/DC Converter with Built-In LDO Regulator In Series plus Voltage Detector Preliminary ! Input Voltage Range ! Output Voltage Range ! APPLICATIONS " CD-R / RW, DVD " HDD " PDAs, portable communication modem


    Original     		PDF XC9510 300kHz, 600kHz, 800mA 600mA XC9510D XC9510H CDRH4D28C

    GENERATOR AUTOMATIC VOLTAGE REGULATOR

    Abstract: Automatic Voltage Regulator block diagram XC9508 XC9509 XC9510 XC9511 DIAGRAM Automatic Voltage Regulator GENERATOR
    Text: LDO Regulator Built-In Synchronous Step-Down DC/DC Converters XC9510 / 11 Series Preliminary June 9, 2003 Ver. 3 ! INPUT VOLTAGE RANGE : ! OUTPUT VOLTAGE RANGE : ! SWITCHING FREQUENCY : ! OUTPUT CURRENT : 2.4V ~ 6.0V DC/DC 0.9 ~ 4.0V ±2% VR 0.9 ~ 4.0V (±2%)


    Original     		PDF XC9510 300kHz, 600kHz, 800mA 400mA XC9510/11 GENERATOR AUTOMATIC VOLTAGE REGULATOR Automatic Voltage Regulator block diagram XC9508 XC9509 XC9511 DIAGRAM Automatic Voltage Regulator GENERATOR

    CDRH4D28C

    Abstract: CDRH5D28 CDRH6D28 CDRH6D38 XC9510 step down Voltage Regulator sop8
    Text: XC9510 Series ETR1007_001 Synchronous Step-Down DC/DC Converter with Built-In LDO Regulator In Series Plus Voltage Detector •GENERAL DESCRIPTION The XC9510 series consists of a step-down DC/DC converter and a high-speed LDO regulator connected in series with the


    Original     		PDF XC9510 ETR1007 800mA CDRH4D28C CDRH5D28 CDRH6D28 CDRH6D38 step down Voltage Regulator sop8

    HP 3070 Manual

    Abstract: HP 3070 series 3 Manual HP 3070 Tester PB-0300 PB05 XAPP113 PAD120 01ZX PB020 SVF pcf
    Text: APPLICATION NOTE Faster Erase Times for XC95216 and XC95108 Devices on HP 3070 Series Testers  XAPP113 July 22, 1998 Version 1.0 Application Note Summary This application note describes an enhanced procedure for utilizing the new faster bulk erase capability of the XC95216 and


    Original     		PDF XC95216 XC95108 XAPP113 XC9500 XC95108. HP 3070 Manual HP 3070 series 3 Manual HP 3070 Tester PB-0300 PB05 PAD120 01ZX PB020 SVF pcf

    XC95108-15TQ100C

    Abstract: XC95108-15PCG84C XC95108 XC95108-20TQ100I XC95108-15TQG100C XC95108-10PQG160I PQ100 PQG160 xc95108 tq100 XC95108-15TQ100I
    Text: XC95108 In-System Programmable CPLD R DS066 v4.4 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates Up to 108 user I/O pins 5V in-system programmable


    Original     		PDF XC95108 DS066 36V18 XC9500 PQ160 XC95108-15TQ100C XC95108-15PCG84C XC95108-20TQ100I XC95108-15TQG100C XC95108-10PQG160I PQ100 PQG160 xc95108 tq100 XC95108-15TQ100I

    XC95108-20TQ100I

    Abstract: XC95108 xc95108 tq100 XC95108-15PC84C XC95108-15TQ100I PC84 XC9500 7PQ100I xc95108-7 XC95108-7PQ100C
    Text: XC95108 In-System Programmable CPLD R DS066 v4.1 August 21, 2003 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates Up to 108 user I/O pins 5V in-system programmable


    Original     		PDF XC95108 DS066 36V18 XC95108-20TQ100I xc95108 tq100 XC95108-15PC84C XC95108-15TQ100I PC84 XC9500 7PQ100I xc95108-7 XC95108-7PQ100C

    XC9500

    Abstract: XC95108
    Text: XC95108 In-System Programmable CPLD  October 28, 1997 Version 2.0 3* Product Specification Features Power Management • • • • • Power dissipation can be reduced in the XC95108 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize


    Original     		PDF XC95108 36V18 PQ100 TQ100 PQ160 84-Pin 100-Pin XC9500

    xc95108

    Abstract: XC95108-7PC84C
    Text: XC95108 In-System Programmable CPLD R DS066 v4.0 June 18, 2003 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates Up to 108 user I/O pins 5V in-system programmable


    Original     		PDF XC95108 DS066 36V18 XC95108-7PC84C

    Untitled

    Abstract: No abstract text available
    Text: – PRODUCT OBSOLETE / UNDER OBSOLESCENCE – k XC9500 In-System Programmable CPLD Family R DS063 v6.0 May 17, 2013 Product Specification Features - Advanced CMOS 5V FastFLASH technology • - Supports parallel programming of multiple XC9500 devices High-performance


    Original     		PDF XC9500 DS063 XC9500 36V18 produ2/10/1999 XC95288. 352-pin XC95216. XCN07010 XCN11010

    PLCC-48 footprint

    Abstract: XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 XC9500 XC9500 pinout
    Text: XC9500 In-System Programmable CPLD Family R December 14, 1998 Version 3.0 1* Features Family Overview • The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system


    Original     		PDF XC9500 PLCC-48 footprint XC95108 XC95144 XC95216 XC95288 XC9536 XC9572 XC9500 pinout

    Untitled

    Abstract: No abstract text available
    Text: HXILINX’ XC95108 In-System Programmable CPLD June 1, 1996 Version 1.0 Preliminary Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins fc N T t0 125 MHz • • • 108 macrocells with 2400 usable gates Up to 108 user I/O pins


    OCR Scan     		PDF XC95108 36V18 84-Pin PQ100 100-Pin TQ100 PQ160 160-Pin PQ100

    xilinx pq-160

    Abstract: No abstract text available
    Text: HXILINX XC95108 In-System Programmable CPLD October 2 8 ,1 9 9 7 Version 2.0 Product Specification Features Power Management • 7.5 ns pin-to-pin logic delays on all pins • fcNT to 125 MHz • • • 108 macrocells with 2400 usable gates Up to 108 user I/O pins


    OCR Scan     		PDF XC95108 PQ100 TQ100 PQ160 84-Pln 100-Pin 160-Pin xilinx pq-160

    xilinx pq100

    Abstract: No abstract text available
    Text: K xilinx XC95108 In-System Programmable CPLD Ju n e 1, 1996 V ersion 1.0 Preliminary Product Specification Features Power Management • • Power dissipation can be reduced in the XC95108 by con­ figuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize


    OCR Scan     		PDF XC95108 36V18 PQ100 TQ100 PQ160 84-Pin 100-Pin 160-Pin PQ100 xilinx pq100

    Untitled

    Abstract: No abstract text available
    Text: HXILINX XC95108 In-System Programmable CPLD December 4, 1998 Version 3.0 Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins fcN T 125 MHz • • • 108 macrocells with 2400 usable gates Up to 108 user I/O pins


    OCR Scan     		PDF XC95108 36V18 PQ100 TQ100 PQ160 84-Pin 100-Pin 160-Pin PQ100

    Untitled

    Abstract: No abstract text available
    Text: HXILINX XC95108 In-System Programmable CPLD June 1,1 9 9 6 Version 1.0 Preliminary Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins foNT to 125 MHz • • • 108 macrocells with 2400 usable gates Up to 108 user I/O pins


    OCR Scan     		PDF XC95108 36V18 84-Pln PQ100 100-Pin TQ100 PQ160 160-Pin PQ100

    Untitled

    Abstract: No abstract text available
    Text: f i XILINX XC95108 In-System Programmable CPLD J a n u a ry , 1 9 9 7 V e rs io n 1.0 Prelim inary Product Specification Features Power Management • 7.5 ns pin-to-pin logic delays on all pins • fcNT to 125 MHz • • • 108 m acrocells with 2400 usable gates


    OCR Scan     		PDF XC95108 36V18 100-Pin 160-Pin PQ100 TQ100 PQ160 XC95108 XC95108F

    Untitled

    Abstract: No abstract text available
    Text: flX IU N X XC95106 In-System Programmable CPLD October 28, 1997 Version 2.0 Product Specification Features Power Management • 7.5 ns pin-to-pin logic delays on all pins • fcNT to ^2.5 MHz • • • 108 macrocells with 2400 usable gates Up to 108 user I/O pins


    OCR Scan     		PDF XC95106 36V18 84-Pin 100-Pin 160-Pin PQ100 TQ100 PQ160 XC95108