Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    UMC 0.18 Search Results

    UMC 0.18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    World transistors and ic

    Abstract: mixed signal fpga datasheet XC4000XV xilinx silicon device
    Text: SHI PPI NG The World’s First 0.25-micron FPGA Family L 8 eading the logic industry with the most advanced semiconductor manufacturing processes, Xilinx, in partnership with United Microelectronics Corporation UMC has developed a new 0.25-micron FPGA process technology. This leading-edge technology is the


    Original     		PDF 25-micron XC4000XV XC40125XV, XC40125XV 18-micron World transistors and ic mixed signal fpga datasheet XC4000XV xilinx silicon device

    RTSX32SU CQ84 PROTO

    Abstract: CQ84 SOC 8A fuse smd RTSX32SU CQ84 rtsx72su RTSX32SU CG624 thermal expansion
    Text: Revision 8 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32SU CQ84 PROTO CQ84 SOC 8A fuse smd RTSX32SU CQ84 rtsx72su RTSX32SU CG624 thermal expansion

    RTSX32SU CQ84 PROTO

    Abstract: RTSX32SU CQ84 RTSX72SU1 SOC 8A fuse smd RTSX32su CG624 thermal expansion
    Text: Revision 9 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32SU CQ84 PROTO RTSX32SU CQ84 RTSX72SU1 SOC 8A fuse smd RTSX32su CG624 thermal expansion

    ChipX

    Abstract: H264 cx-5900
    Text: Product Brief CX5900 0.18 µm Standard Cell ASIC/Soc Product Description The CX5900 ASIC and System on Chip SoC offering from ChipX combines the well-proven UMC standard six-metal 0.18-µm deep submicron process technology with a rich portfolio of silicon-proven processors, memory structures, analog, I/O and digital IP, and advanced


    Original     		PDF CX5900 CX5900 1-800-95-CHIPX 0340-5K-070-A ChipX H264 cx-5900

    RTSX32SU

    Abstract: RTSX32SU CQ84 rtsx72su RTSX32 RTSX-SU 1/RTSX32su CC256 PRB-1 actel 1020 datasheet CG624
    Text: Revision 7 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 MIL-ST00 RTSX32SU RTSX32SU CQ84 rtsx72su RTSX32 RTSX-SU 1/RTSX32su CC256 PRB-1 actel 1020 datasheet CG624

    RTSX72

    Abstract: No abstract text available
    Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX72

    RTSX32SU CQ84

    Abstract: Silicon Sculptor II RTSX32SU actel 1020
    Text: v2.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32SU CQ84 Silicon Sculptor II RTSX32SU actel 1020

    RTSX32SU

    Abstract: RTSX32SU CQ84 Actel a54sx72a tid RTSX72SU RTSX-SU actel 1020 Silicon Sculptor II actel 1020 datasheet RT54SX E11213
    Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32SU RTSX32SU CQ84 Actel a54sx72a tid RTSX72SU RTSX-SU actel 1020 Silicon Sculptor II actel 1020 datasheet RT54SX E11213

    RTSX32SU

    Abstract: RTSX32 PQFP die size C5249 bst r16 166 P790 actel 1020 datasheet A54SX72A CC256 CQ208
    Text: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32SU RTSX32 PQFP die size C5249 bst r16 166 P790 actel 1020 datasheet A54SX72A CC256 CQ208

    RTSX72

    Abstract: RTSX72SU A54SX72A TID "tristate buffer" A54SX32S-PQ208 RT54SXproto
    Text: Advanced v0.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX72 RTSX72SU A54SX72A TID "tristate buffer" A54SX32S-PQ208 RT54SXproto

    SMD ARAY

    Abstract: No abstract text available
    Text: Revision 6 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 MIL-STD-883B SMD ARAY

    SU 177

    Abstract: RTSX32SU A54SX72* radiation Actel a54sx72a tid antifuse A54SX72A CC256 CG624 CQ208 CQ256
    Text: Advanced v0.3 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 SU 177 RTSX32SU A54SX72* radiation Actel a54sx72a tid antifuse A54SX72A CC256 CG624 CQ208 CQ256

    RTSX32su

    Abstract: Actel a54sx72a tid Silicon Sculptor II
    Text: v2.2 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32su Actel a54sx72a tid Silicon Sculptor II

    RTSX32su

    Abstract: RTSX32SU CQ84 RTSX72SU
    Text: v2.0 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTSX32su RTSX32SU CQ84 RTSX72SU

    Xilinx counter

    Abstract: working of adopter XC4036XV
    Text: XILINX NEWS BRIEF 1GHz Performance Milestone – 0.18µ, 1.8V FPGA Xilinx recently achieved 1GHz performance in a prototype 0.18µ FPGA, using a frequency counter design. These FPGAs, derivatives of the XC4036XV family, were part of a mask set used as the process driver for our new 0.18µ technology.


    Original     		PDF XC4036XV Xilinx counter working of adopter

    verilog code for apb

    Abstract: verilog code for amba apb bus AMBA APB bus spdif input processor bit stream verilog code for amba apb master verilog code for transmitter IEC-60958 spdif input spdif input processor FIFO amba apb
    Text: Conforms to the IEC 60958 International Standard Programmable: supports both Receiver and Transmitter modes SPDIF-APB Data mode capabilities: Digital Audio Interface Core o Supports sample rates from 3kHz to 192kHz with 98MHz SPDIF system clock o 20/24 bits per sample


    Original     		PDF 192kHz 98MHz verilog code for apb verilog code for amba apb bus AMBA APB bus spdif input processor bit stream verilog code for amba apb master verilog code for transmitter IEC-60958 spdif input spdif input processor FIFO amba apb

    samsung 10K filing SEC

    Abstract: samsung electronics 10K filing SEC UNITED MICROELECTRONICS CORPORATION United Silicon United Technologies Mostek fabco m 426 mostek system development board Jabil Circuit
    Text: SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 _ FORM 10-K Mark One [x] Annual report pursuant to section 13 or 15(d) of the securities exchange act of 1934 For the fiscal year ended April 1, 2000, or [ ] Transition report pursuant to section 13 or 15(d) of the securities exchange act of 1934


    Original     		PDF

    Andrew

    Abstract: RF 8SF
    Text: Inside the New Computer Industry • January 2001 • Andrew Allison The 0.13 micron Race It appears that 0.13 micron gamesmanship is widespread: Despite the fact that I checked the 0.13 micron story twice with Motorola, what that company is really shipping Intelligence, December


    Original     		PDF

    TSMC 0.35Um

    Abstract: 80C515C ocds 0.35Um tsmc 8051 mcs51 ASM51 MCS51 R8051XC2 T8051 TSMC 0.25Um
    Text: 100% MCS51 compliant Central Processing Unit T8051 Tiny 8051-Compatible Microcontroller Core A semiconductor IP core that implements an extremely small 8-bit microcontroller executing the ASM51 instruction set. It includes peripherals for serial communication, a


    Original     		PDF MCS51® T8051 8051-Compatible ASM51 R8051XC2 T8051 TSMC 0.35Um 80C515C ocds 0.35Um tsmc 8051 mcs51 MCS51 TSMC 0.25Um

    verilog code for parallel transmission

    Abstract: verilog code for dma controller dram verilog model flash controller verilog code crc verilog code 16 bit ATA-33 DVD read writer BLOCK diagram dvd writer block diagram verilog code for Flash controller
    Text: Complies with ATA-7 Standard Supports one or two IDE devices ATAIF ATA-7/IDE Host Controller Core Implements a host controller for non-volatile memory devices using the parallel interface known as ATA Advanced Technology Attachment , IDE (Integrated Drive Electronics),


    Original     		PDF

    United Silicon

    Abstract: No abstract text available
    Text: COLUMN XILINX NEWS Recent press releases and announcements, with Web references for further information. Press Releases Xilinx Launches Third-Party Design Consulting Program November 16, 1998 - Xilinx today announced the creation of the Xilinx Program for Engineering Resources from Third Parties


    Original     		PDF

    MC68000

    Abstract: AMBA AHB bus arbiter MC68000 opcodes
    Text: Control Unit − 16-bit two levels instruction decoder C68000-AHB − Three levels instruction queue 32-bit Microprocessor Core 55 instructions and 14 address modes Supervisor and User mode − Independent stack pointer for each mode Users registers Implements a powerful 32-bit microprocessor is derived from the Motorola MC68000


    Original     		PDF 16-bit C68000-AHB 32-bit MC68000 C68000-AHB IEEE1149 MC68000 AMBA AHB bus arbiter MC68000 opcodes

    verilog code for 32 BIT ALU multiplication

    Abstract: 16 BIT ALU design with verilog code verilog code for 32 BIT ALU implementation 16 BIT ALU design with verilog hdl code 8 BIT ALU design with verilog code verilog code for ALU implementation verilog code for 32 BIT ALU division 8 BIT microprocessor design with verilog hdl code C68000 M6800
    Text: Control Unit o 16-bit two levels instruction decoder C68000 16-bit Microprocessor Core o Three levels instruction queue 55 instructions and 14 address modes Supervisor and User mode o Independent stack for both modes Users registers The C68000 is core of a powerful 16/32-bit microprocessor and is derived from the Motorola MC68000 microprocessor. The C68000 is a fully functional 32-bit internal and 16bit external equivalent for the MC68000. The C68000 serves interrupts and exceptions,


    Original     		PDF 16-bit C68000 C68000 16/32-bit MC68000 32-bit 16bit MC68000. verilog code for 32 BIT ALU multiplication 16 BIT ALU design with verilog code verilog code for 32 BIT ALU implementation 16 BIT ALU design with verilog hdl code 8 BIT ALU design with verilog code verilog code for ALU implementation verilog code for 32 BIT ALU division 8 BIT microprocessor design with verilog hdl code M6800

    UMX-XXX-D16

    Abstract: 2505U
    Text: CONFIDENTIAL in cu in S B o in - 0 .5 0 0.50 - 0 .4 2 0 0.385­ umc 0.285— - 0 .3 2 0 UMX-XXX-D16 0.185 - - 0.220 - 0.120 L/C # (wwyy) 0.085 0.00 - I I I I I o -0.00 in o o 4 Breakout tab detail All C o ntact Dimensions 0.148 — 0.100 0.048— 0.00 DETAIL A


    OCR Scan     		PDF UMX-XXX-D16 UP-D16 UMX-XXX-D16 2505U