TRA14
Abstract: CBF 420 05801 ALI-25 SALI-25C TIC85 701BR
Text: CUBIT Device CellBus Bus Switch TXC-05801 DATA SHEET FEATURES DESCRIPTION • UTOPIA or ALI-25 physical-layer cell interface • Inlet-side address translation and routing header insertion, using external SRAM • Programmable OAM cell routing • CellBus bus access request, grant reception and
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TXC-05801
ALI-25
TXC-05801-MB
TRA14
CBF 420
05801
SALI-25C
TIC85
701BR
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ALI-25
Abstract: ALI-25C circuit diagram of queuing with seven segment
Text: CUBIT Device CellBus Switch TXC-05801 DATA SHEET FEATURES DESCRIPTION • UTOPIA or ALI-25 physical-layer cell interface • Inlet-side address translation and routing header insertion, using external SRAM • Programmable OAM cell routing • CellBus access request, grant reception and bus
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TXC-05801
ALI-25
TXC-05801-MB
ALI-25C
circuit diagram of queuing with seven segment
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Untitled
Abstract: No abstract text available
Text: CUBIT-3 Device CellBus Bus Switch TXC-05804 DATA SHEET PRODUCT PREVIEW DESCRIPTION CUBIT®-Pro The CUBIT-3 is a single-chip solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus® architecture. Such systems are
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TXC-05804
TXC-05802)
TXC-05810)
8/16-bit)
TXC-05804-MB
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3F SOT3
Abstract: No abstract text available
Text: CUBIT-3 Device CellBus Bus Switch TXC-05804 DATA SHEET CUBIT®-Pro The CUBIT-3 is a single-chip VLSI solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus® architecture. Such systems are constructed from a number of CellBus devices, all
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TXC-05804
TXC-05802B)
CUBIT-622
TXC-05805)
TXC-05810)
8/16-bit)
TXC-05804-MB
3F SOT3
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Untitled
Abstract: No abstract text available
Text: CUBIT-3 Device CellBus Bus Switch TXC-05804 DATA SHEET FEATURES DESCRIPTION • Interoperable with CUBIT®-Pro TXC-05802B , ASPEN (TXC-05810) UTOPIA Level 2 interface (8/16-bit) with support for 16 ports • Supports dual OC-3 steady state bidirectional
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TXC-05804
TXC-05802B)
TXC-05810)
8/16-bit)
TXC-05804-MB
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Untitled
Abstract: No abstract text available
Text: CUBIT-3 Device CellBus Bus Switch TXC-05804 DATA SHEET FEATURES DESCRIPTION • Interoperable with CUBIT®-Pro TXC-05802B , ASPEN (TXC-05810) UTOPIA Level 2 interface (8/16-bit) with support for 16 ports • Supports dual OC-3 steady state bidirectional
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TXC-05804
TXC-05802B)
TXC-05810)
8/16-bit)
TXC-05804-MB
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TC514400
Abstract: TCWP
Text: • ^ Sill - . ■■- - - ^ M P M R m Ê t o -.i— ■ SfflMfaWWW« mtssSsm M — l ■ ¡■ ¡ p s i 1,048,576 WORD x 4 BIT DYNAMIC RAM * This is advanced information and specifications are subject to change without notice. DESCRIPTION The TC514400J/Z is the new generation dynamic RAM organized 1,048,576 words by 4
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TC514400J/Z
TC514400J/Z-80
TC514400J/Z--10
TC514400
TCWP
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HY524400
Abstract: No abstract text available
Text: HY524400 Series »HYUNDAI 1 M x 4-bit CMOS DRAM DESCRIPTION The HY524400 is the new generation and fast dynamic RAM organized 1,048,576 x 4 bits. The HY524400 utilizes CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins
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HY524400
1AC04-10-MAY94
HY524400J
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Untitled
Abstract: No abstract text available
Text: PRELIM IN ARY DATA S H E E T N EC MOS INTEGRATED CIRCUIT M C -4 2 1 0 0 0 A D 7 2 F 1M-WORDBY 72-BIT DYNAMIC RAM MODULE FAST PAGE MODE ECC Description The MC-421000AD72F is a 1 048 576 words by 72 bits dynamic RAM module on which 4 pieces Of 16M DRAM ( li P D 4218160) and 2 pieces of 4M DRAM ( UPD424400)
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72-BIT
MC-421000AD72F
UPD424400)
M168S-50A4
b4E7S25
005fl27b
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Untitled
Abstract: No abstract text available
Text: •HYUNDAI HY51V4170B S e rie s 256K X 16-blt CMOS DRAM with 2 WE PRELIMINARY DESCRIPTION The HY51V4170B is the new generation and fast dynamic RAM organized 262,144 x 16-bit configuration employing advanced submicron CMOS process technology and advanced circuit design technique to achieve
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HY51V4170B
16-blt
16-bit
400mil
40pin
40/44pin
72mW21
1AC22-00-MAY94
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Untitled
Abstract: No abstract text available
Text: MICRO N T E C H N O L O G Y INC b l l l S H I D D D 4 36 S Ö17 • URN 55E D ADVANCE MT4C8512/3 L 512K X 8 DF5AM MICRON 512K x 8 DRAM LOW POWER, EXTENDED REFRESH FEATURES • Industry standard x8 pinouts, timing, functions and packages • Address entry: 10 row addresses, nine column
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MT4C8512/3
MT4C8513
024-cycle
128ms
350mW
MT4C8512/3L
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Untitled
Abstract: No abstract text available
Text: H Y 5 1 V 4 4 0 3 B • • H Y U N D A I S e r ie s IM x 4-bit CMOS DRAM with4CAS PRELIMINARY DESCRIPTION The HY51V4403B is the new generation and fast dynamic RAM organized 1,048,576 x 4-bit. The HY51V4403B has four CASs CAS0-3 which control corresponding data I/O port in conjunction with OE(eg. CASO controls DQO,
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HY51V4403B
050f1
1AC1S-00-MAY94
HY51V4403BJ
HY51V4403BU
HYS1V4403BSU
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Untitled
Abstract: No abstract text available
Text: NEC MOS INTEGRATED CIRCUIT juPD42S4400L, 424400L 3.3 V OPERATION 4 M BIT DYNAMIC RAM 1 M-WORD BY 4-BIT, FAST PAGE MODE Description The /¿PD42S4400L, 424400L are 1 048 576 w ords by 4 bits dynam ic CMOS RAMs. The fast page mode capability realize high speed access and low power consumption.
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juPD42S4400L
424400L
PD42S4400L,
424400L
PD42S4400L
26-pin
//PD42S4400L
PD42S4400L
cycles/128
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DML D01
Abstract: No abstract text available
Text: HYUNDAI HY514810B Series 5 1 2 K x 8 - b it C M O S DRAM w ith W r ite -P e r - B II PRELIMINARY DESCRIPTION The HY51481 OB is the new generation and fast dynamic RAM organized 524,288 x 8-bits. The HY51481 OB utilizes Hyundai's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating
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HY514810B
HY51481
1AC19-00-MAY94
HY514810BJC
HY514810BUC
HY514810BSUC
HY514810BTC
DML D01
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Untitled
Abstract: No abstract text available
Text: ••HYUNDAI H Y 5 1 1 7 4 1 0 S e r ie s 4M X 4-bit C M O S DRAM with Write-Per-Bit DESCRIPTION The HY5117410 is the new generation and fast dynamic RAM organized 4,194,304 x 4-bit with function of Write-Per-Bit. The HY5117410 utilizes Hyundai’s CMOS silicon gate process technology as well as advanced
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HY5117410
1AD06-10-MAY94
HY5117410JC
HY5117410UC
HY5117410TC
HY5117410LTC
HY5117410RC
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Untitled
Abstract: No abstract text available
Text: DATA SHEET NEC / MOS INTEGRATED CIRCUIT MP D 4 2 1 6 4 0 5 16M-BIT DYNAMIC RAM 4M-WORD BY 4-BIT, HYPER PAGE MODE DESCRIPTION The fiPD4216405 is a 4 194 304 words by 4 bits dynamic CMOS RAM with optional hyper page mode. Hyper page mode is a kind of the page mode and is useful for the read operation.
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16M-BIT
fiPD4216405
tPD4216405
26-pin
cycles/64
/1PD4216405-50
016to
D0S71SS
b45755S
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Untitled
Abstract: No abstract text available
Text: MT4LC2M8E7 L 2 MEG X 8 DRAM M IC R O N 2 MEG x 8 DRAM DRAM 3.3V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH PIN ASSIGNMENT (Top View) • Industry-standard x8 pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single +3.3V ±0.3V power supply
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150mW
048-cycle
28-Pin
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Untitled
Abstract: No abstract text available
Text: “HYUNDAI HY51V4810B Series 5 1 2 K x 8 -b tt CM O S DRAM w it h W r it e - P e r - B it PRELIMINARY DESCRIPTION The HY51V4810B is the new generation and fast dynamic RAM organized 524,288 x 8-bits. The HY51V4810B utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide
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HY51V4810B
HY51V4810B
1AC20-00-MAY94
HY51V4810BJC
HY51V4810BSUC
HY51V4810BTC
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auto tran 600
Abstract: No abstract text available
Text: t h a n S w it c h „ CUBIT Device CellBus Bus Switch TXC-05801 X- DATA SHEET FEATURES DESCRIPTION • UTOPIA or ALI-25 physical-layer cell Interface CUBIT Is a single-chip solution for Implementing low-cost ATM multiplexing and switching systems,
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ALI-25
TXC-05801-MB
auto tran 600
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Untitled
Abstract: No abstract text available
Text: • TRAN ^ k 1004152 0007020 104 ■ CUBIT Device «g*, »* jiüüM R. > ,.M V. CellBus Bus Switch TXC-05801 DATA SHEET DESCRIPTION FEATURES CUBIT is a single-chip solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus bus architecture. Such systems
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TXC-05801
37-line
TXC-05801-MB
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Untitled
Abstract: No abstract text available
Text: C U B IT Device C eîîB us Switch TXC-05801 DATA SH EE T FEATURES DESCRIPTION • U TO PIA or A LI-25 physical-layer cell interface C U B IT is a single-chip solution fo r im plem enting low -cost ATM m ultiplexing and sw itching system s, based on the CellBus architecture. Such system s are
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TXC-05801
LI-25
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Untitled
Abstract: No abstract text available
Text: tmän S w it c h CUBIT-Pro Device CellBus Bus Switch TXC-05802 S x- DATA SHEET DESCRIPTION FEATURES • UTOPIA and 16-Bit ATM or PHY or ALI-25 PHY Layer cell interfaces • Inlet-side address translation and routing header insertion, using external SRAM of up to 256 kB
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TXC-05802
16-Bit
ALI-25
TXC-05802-MB
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NATIONAL SEMICONDUCTOR MARKING CODE sot
Abstract: ALI-25 ALI-25C SALI-25C TXC-05802-TM1 marking WR4 SOT
Text: t r a n S w it c h CUBIT-Pro Device CellBus Bus Switch TXC-05802 & X- DATA SHEET DESCRIPTION FEATURES • UTOPIA and 16-Bit ATM or PHY or ALI-25 PHY Layer cell interfaces • Inlet-side address translation and routing header insertion, using external SRAM of up to 256 kB
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TXC-05802
16-Bit
ALI-25
TXC-05802-MB
NATIONAL SEMICONDUCTOR MARKING CODE sot
ALI-25C
SALI-25C
TXC-05802-TM1
marking WR4 SOT
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7 pin ic cp43
Abstract: ALI-25 ALI-25C rh30100
Text: CUBIT-Pro Device t r a n S w it c h CellBus Bus Switch TXC-05802 X- DATA SHEET DESCRIPTION FEATURES • UTOPIA and 16-Bit ATM or PHY or ALI-25 PHY Layer cell interfaces • Inlet-side address translation and routing header insertion, using external SRAM of up to 256 kB
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TXC-05802
16-Bit
ALI-25
16BMODE,
32USER
TXC-05802-MB
7 pin ic cp43
ALI-25C
rh30100
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