ADuM1250
Abstract: MS-012-AA PWD21
Text: Hot Swappable, Dual I2C Isolators ADuM1250/ADuM1251 FUNCTIONAL BLOCK DIAGRAMS VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE 7 SDA2 SCL1 3 DECODE ENCODE 6 SCL2 GND1 4 ENCODE DECODE 5 GND2 Figure 1. ADuM1250 VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE
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ADuM1250/ADuM1251
ADuM1250
D06113-0-5/10
ADuM1250
MS-012-AA
PWD21
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PDF
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CDC337
Abstract: CDC337DBLE CDC337DW CDC337DWG4 CDC337DWR CDC337DWRG4 CDC337NS MS-013
Text: CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 D D D D D D D DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs
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Original
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CDC337
SCAS330B
48-mA
CDC337
CDC337DBLE
CDC337DW
CDC337DWG4
CDC337DWR
CDC337DWRG4
CDC337NS
MS-013
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PDF
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CDC318
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
CDC318
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PDF
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c.i 9409
Abstract: No abstract text available
Text: CDC339 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS331 – DECEMBER 1992 – REVISED MARCH 1994 D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight
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Original
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CDC339
SCAS331
48-mA
CLC339DBLE
CDC339DBR
CDC339DW
CDC339DWR
c.i 9409
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 D D D D D D D DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs
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Original
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CDC337
SCAS330B
48-mA
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PDF
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CDC337
Abstract: MS-013
Text: CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 D D D D D D D DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs
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Original
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CDC337
SCAS330B
48-mA
CDC337
MS-013
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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Original
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CDC318
18-LINE
SCAS587B
1-to-18
MIL-STD-883,
48-Pin
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PDF
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48-PIN
Abstract: CDC318A CDC318ADL CDC318ADLG4
Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
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Original
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CDC318A
18-LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
CDC318A
CDC318ADL
CDC318ADLG4
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC339 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS331 – DECEMBER 1992 – REVISED MARCH 1994 D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight
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Original
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CDC339
SCAS331
48-mA
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PDF
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Untitled
Abstract: No abstract text available
Text: Hot Swappable, Dual I2C Isolators ADuM1250/ADuM1251 Data Sheet APPLICATIONS VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE 7 SDA2 SCL1 3 DECODE ENCODE 6 SCL2 GND1 4 ENCODE DECODE 5 GND2 06113-001 FUNCTIONAL BLOCK DIAGRAMS Bidirectional I2C communication
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Original
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ADuM1250/ADuM1251
D06113-0-3/14
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PDF
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Untitled
Abstract: No abstract text available
Text: FEATURES FUNCTIONAL BLOCK DIAGRAM isoPower integrated, isolated dc-to-dc converter Regulated 3.15 V to 5.25 V output Up to 150 mW output power High common-mode transient immunity: >25 kV/µs iCoupler integrated I2C digital isolator Bidirectional I2C communication
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Original
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20-lead
RS-20)
ADM3260ARSZ
ADM3260ARSZ-RL7
EVAL-ADM3260EBZ
RS-20
ADM3260
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PDF
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48-PIN
Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications
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Original
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CDC318A
18LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
CDC318A
CDC318ADL
CDC318ADLG4
CDC318ADLR
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PDF
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PWD21
Abstract: adum1250 TPLH12
Text: Hot Swappable, Dual I2C Isolators ADuM1250/ADuM1251 APPLICATIONS 2 Isolated I C, SMBus, or PMBus interfaces Multilevel I2C interfaces Power supplies Networking Power-over-Ethernet FUNCTIONAL BLOCK DIAGRAMS VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE 7
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Original
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ADuM1250/ADuM1251
CM1251ARZ1
ADuM1251ARZ-RL71
D06113-0-12/09
PWD21
adum1250
TPLH12
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PDF
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ADUM1250ARZ
Abstract: PWD21 adum1250
Text: Hot Swappable Dual I2C Isolators ADuM1250/ADuM1251 APPLICATIONS 2 Isolated I C, SMBus, or PMBus interfaces Multilevel I2C interfaces Power supplies Networking Power-over-Ethernet FUNCTIONAL BLOCK DIAGRAMS VDD1 1 DECODE ENCODE 8 VDD2 SDA1 2 ENCODE DECODE 7
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Original
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ADuM1250/ADuM1251
ADuM1250ARZ
ADuM1250ARZ-RL71
ADuM1251ARZ1
ADuM1251ARZ-RL71
D06113-0-6/07
PWD21
adum1250
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PDF
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K3638
Abstract: 4Y04
Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
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Original
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CDC318A
18-LINE
SCAS614A
1-to-18
100-MHz
MIL-STD-883,
48-Pin
K3638
4Y04
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PDF
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CDC339
Abstract: No abstract text available
Text: CDC339 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS331 – DECEMBER 1992 – REVISED MARCH 1994 D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight
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Original
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CDC339
SCAS331
48-mA
CDC339
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC339 CLOCK DRIVER WITH 3ĆSTATE OUTPUTS SCAS331 − DECEMBER 1992 − REVISED MARCH 1994 D Low Output Skew, Low Pulse Skew for D D D D D D DB OR DW PACKAGE TOP VIEW Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs
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Original
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SCAS331
CDC339
48-mA
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PDF
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3014 LED
Abstract: MARKING CFK l1801-1 SVI 3003 W2T marking 103 c1k end of life car tyres T-17911 54ls162 jill2
Text: MIL-M-38510/315C 17 Ja n u a r y 1984 SUPERSEDING M I L - M - 3 8 5 1 0 / 3 1 5B 16 April 1981 MILITARY MICROCIRCUITS, SPECIFICATION DIGITAL, T T L , COUNTERS, LOW-POWER MONOLITHIC T hi s s p e c i f i c a t i o n is a p p r o v e d ments and Agencies of th e
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OCR Scan
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MIL-M-38510/315C
MIL-M-38510/315B
MIL-M-38510.
54LS163A
54LS19Ã
MIL-M-38510/315C
5-040/A
3014 LED
MARKING CFK
l1801-1
SVI 3003
W2T marking
103 c1k
end of life car tyres
T-17911
54ls162
jill2
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PDF
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PWL-6
Abstract: TTC 5200
Text: ! MIL-M-38510/490A 11 September 1986 SU PERSED lk— MI L - M-38 510 / 490 US AF I D e c e m b e r 1981 I QUAL I F I CATION I ¡REQUIREMENTS I IREMOVED_ I MILITARY SPECIFICATION M I C R O C I R C U I T S , D I G I T A L , N-CHANNEL, S I L I C O N
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OCR Scan
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MIL-M-38510/490A
l985---
MIL-M-38510.
forMIL-M-39510
PWL-6
TTC 5200
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PDF
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80c85
Abstract: HS80C85
Text: S H S - 5 4 C 1 3 8 R H R a d ia t io n H a r d e n e d February 1996 3 - L in e to 8 - L in e D e c o d e r /D e m u lt ip le x e r Features Pinouts • Devices QML Qualified in Accordance With MIL-PRF-38535 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP
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OCR Scan
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MIL-PRF-38535
IL-STD-1835
CDIP2-T16
HS-54C
0b573D
80c85
HS80C85
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PDF
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sidd
Abstract: SA2995 Harris top marking
Text: 33 fcKHffiSR HS-54C138RH Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer December 1992 Pinouts Features 16 PIN DIP CASE OUTLINE D2, CONFIGURATION 3 TOP VIEW • Radiation Hardened EPI-CMOS - Total Dose 1 x 10s RAD Si - Latch-Up Immune > 1 x 1012 RAD(Si)/s
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OCR Scan
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HS-54C138RH
SA2995
80C85RH
HS-54C138RH
sidd
SA2995
Harris top marking
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PDF
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RH-1750
Abstract: RH1750 qml-38535 PLH23 PHL27
Text: REVISIONS LTR DESCRIPTION DATE APPROVED YR-MO-DA REV SHEET REV SHEET 15 16 17 REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE 18 19 20 21 22 23 24
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OCR Scan
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5962-E214-95
T00470Ã
MIL-BUL-103.
MIL-BUL-103
RH-1750
RH1750
qml-38535
PLH23
PHL27
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PDF
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CDC337
Abstract: MS-013
Text: CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SC AS 330B - D EC E M B E R 1990 - REVISED O C TO BE R 1998 • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications • TTL-Compatible Inputs and CMOS-Compatible Outputs • DW PACKAGE
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OCR Scan
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CDC337
SCAS330B
-48-mA
48-mA
MS-013
MS-013
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PDF
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Untitled
Abstract: No abstract text available
Text: HS-54C138RH S em iconductor Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer February 1996 Pinouts Features • Devices QML Qualified in Accordance With MIL-PRF-38535 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE SBDIP MIL-STD-1835 CDIP2-T16 • Detailed Electrical and Screening Requirements are
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OCR Scan
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HS-54C138RH
MIL-PRF-38535
MIL-STD-1835
CDIP2-T16
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PDF
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