4.2V
Abstract: and gate d3c F100K SY100S317 SY100S317FC SY100S317JC SY100S317JCTR
Text: TRIPLE 2-WIDE OA/OAI GATE FEATURES SY100S317 FINAL DESCRIPTION • Max. propagation delay of 900ps ■ IEE min. of –48mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ Internal 75KΩ input pull-down resistors
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SY100S317
900ps
F100K
24-pin
28-pin
SY100S317
CONFIGURA0S317FC
F24-1
SY100S317JC
J28-1
4.2V
and gate d3c
F100K
SY100S317FC
SY100S317JC
SY100S317JCTR
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F100K
Abstract: SY100S317 SY100S317FC SY100S317JC SY100S317JCTR
Text: TRIPLE 2-WIDE OA/OAI GATE FEATURES SY100S317 DESCRIPTION • Max. propagation delay of 900ps ■ IEE min. of –48mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ Internal 75KΩ input pull-down resistors
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Original
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PDF
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SY100S317
900ps
F100K
24-pin
28-pin
SY100S317
SY100S317FC
F24-1
SY100S317JC
J28-1
F100K
SY100S317FC
SY100S317JC
SY100S317JCTR
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F100K
Abstract: SY100S317 SY100S317FC SY100S317FCTR SY100S317JC SY100S317JCTR
Text: TRIPLE 2-WIDE OA/OAI GATE Micrel, Inc. FEATURES SY100S317 SY100S317 DESCRIPTION • Max. propagation delay of 900ps ■ IEE min. of –48mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity
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Original
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PDF
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SY100S317
900ps
F100K
24-pin
28-pin
SY100S317
M9999-032206
F100K
SY100S317FC
SY100S317FCTR
SY100S317JC
SY100S317JCTR
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Untitled
Abstract: No abstract text available
Text: * TRIPLE 2-WIDE OA/OAI GATE SYNERGY SY100S317 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 900ps Iee min. o f-48 m A Extended supply voltage option: V ee = -4.2V to -5.5V The S Y 100S 317 is a set of ultra-fast, triple 2-w ide OR/ AND gates designed for use in high-perform ance ECL
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SY100S317
900ps
75Ki2
F100K
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F100K
Abstract: SY100S317 SY100S317DC SY100S317FC ez 623
Text: « Ä TRIPLE 2-WIDE OA/OAi g a t e SYNERGY s y io o s 317 SE M IC O N D U C TO R FEATURES DESCRIPTION I Max. propagation delay of 900ps The S Y 100S 317 is a set of ultra-fast, triple 2-w ide OR/ AND gates designed for use in high-perform ance ECL system s. T his device offers both true and com plem ent
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OCR Scan
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PDF
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SY100S317
900ps
-48mA
F100K
D00E173
SY100S317DC
D24-1
SY100S317FC
F24-1
F100K
SY100S317
ez 623
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Untitled
Abstract: No abstract text available
Text: * TRIPLE 2-WIDE OA/OAI GATE SYNERGY SY100S317 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S317 is a set of ultra-fast, triple 2-w ide OR/ AND gates designed fo r use in high-perform ance ECL system s. This device offers both true and com plem ent outputs. The inputs on this device have 75K£2 pull-down
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OCR Scan
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PDF
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SY100S317
900ps
SY100S317
F100K
24-pin
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Untitled
Abstract: No abstract text available
Text: ÏN SYNERGY T R IP L E 2 -W ID E O A /O A I G A TE SY100S317 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 900ps Ie e The S Y 100S 317 is a set of ultra-fast, triple 2-wide OR/ AND gates designed for use in high-perform ance ECL system s. This device offers both true and com plem ent
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OCR Scan
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PDF
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SY100S317
900ps
75Ki2
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Untitled
Abstract: No abstract text available
Text: V * TRIPLE 2-WIDE OA/OAI GATE SYNERGY SY100S317 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 900ps The SY100S 317 is a set of ultra-fast, triple 2-w ide OR/ AND gates designed for use in high-perform ance ECL system s. T his device offers both true and com plem ent
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OCR Scan
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PDF
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SY100S317
900ps
SY100S
f-48m
F100K
10D13A1
SY100S317DC
D24-1
SY100S317FC
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OA910
Abstract: No abstract text available
Text: S YN ER G Y T R IP L E 2-W iD t 1 Ä /O A I HAT F S E M IC O N D U C T O R B ^aS Z E FE A T U R E S • Max. propagation delay of 900ps ■ I e e min. of -48mA ■ Extended supply voltage option: VEE = -4.2V to -5.5V ■ Voltage and temperature compensation for
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OCR Scan
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PDF
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900ps
-48mA
F100K
24-pin
28-pin
SY100S317
SY100S317DC
SY100S317FC
SY100S317JC
OA910
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