Untitled
Abstract: No abstract text available
Text: Prototyping Microsemi Rad-Tolerant Devices Microsemi™ Prototyping CQFP PACKAGE Aldec RTAX-S/SL Prototyping Adaptors RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S CQ208 CCGA/LGA PACKAGE Aldec and Microsemi have joined together, offering a new, innovative,
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RTAX250S/SL
RTAX1000S/SL
RTAX2000S/SL
RTAX4000S
CG624
CQ352
CG1152
CG1272
RTSX32SU
RTSX72SU
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1553b VHDL
Abstract: Actel 1553b fpga 1553B transistor BC 584 MIL-STD-1553B FPGA RT MIL-STD-1553B ACTEL FPGA manchester verilog decoder vhdl code manchester encoder mil-std-1553b SPECIFICATION transistor BC 490
Text: Core1553BBC MIL-STD-1553B Bus Controller Product Summary • Intended Use • 1553B Bus Controller BC • DMA Backend Interface to External Memory Synthesis and Simulation Support Key Features • • • • • • Supports MIL-STD-1553B Interfaces to External RAM
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Core1553BBC
MIL-STD-1553B
1553B
MIL-STD-1553B
128kbytes
Core1553BRT
1553b VHDL
Actel 1553b
fpga 1553B
transistor BC 584
MIL-STD-1553B FPGA
RT MIL-STD-1553B ACTEL FPGA
manchester verilog decoder
vhdl code manchester encoder
mil-std-1553b SPECIFICATION
transistor BC 490
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LGA 478 SOCKET PIN LAYOUT
Abstract: RTAX2000
Text: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg
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TM1019
LGA 478 SOCKET PIN LAYOUT
RTAX2000
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RTAX2000
Abstract: schematic diagram 2 sc 1020 RTAX1000 RTAX250 Synplify tmr RTAX2000S
Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
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TM1019
com/documents/CQ352FPGA
RTAX2000
schematic diagram 2 sc 1020
RTAX1000
RTAX250
Synplify tmr
RTAX2000S
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RTAX2000
Abstract: TB125 24mA-drive 352-Pin
Text: RTAX-S RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment Clamp Diode Hot Insertion 5V Tolerance Input Buffer Output Buffer LVTTL No Yes No Enabled/Disabled 3.3V PCI Yes No Yes1 Enabled/Disabled LVCMOS2.5V No Yes
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JESD8-11)
RTAX2000
TB125
24mA-drive
352-Pin
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RTAX2000
Abstract: footprint cqfp 280 RTAX1000S actel cqfp 84
Text: A dv an c ed v0 .5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
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TM1019
RTAX2000
footprint cqfp 280
RTAX1000S
actel cqfp 84
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56 pin edac connector
Abstract: PCB footprint cqfp 132 Silicon Sculptor II ACTEL CCGA 624 mechanical
Text: v2.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
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TM1019
56 pin edac connector
PCB footprint cqfp 132
Silicon Sculptor II
ACTEL CCGA 624 mechanical
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RTAX2000
Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
Text: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg
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TM1019
RTAX2000
rtax4000
CDB 455 C34
IO358
DIODE SMD V05
128X3
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RTAX1000SL
Abstract: RTAX1000S RTAX1000S-SL RTAX250SL RTAX2000SL RTAX2000S RTAX250S RTAX4000S 56 pin edac connector
Text: RTAX-S/SL RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment 3.3 V LVTTL Clamp Diode Hot Insertion / Cold Sparing 1 Yes 5V Tolerance Input Buffer Output Buffer No 1 Yes Enabled/Disabled Enabled/Disabled 3.3 V PCI
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JESD8-11)
RTAX1000SL
RTAX1000S
RTAX1000S-SL
RTAX250SL
RTAX2000SL
RTAX2000S
RTAX250S
RTAX4000S
56 pin edac connector
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pressure sensor MATLAB program
Abstract: actel rad pressure sensor 90nm cmos RTAX250S-1000S
Text: A passion for performance. Digital and Mixed-Signal custom, semi-custom, off-the-shelf designs with Aeroflex Gaisler IP Guaranteed radiation performance QML-V, QML-Q, military, medical, industrial grades Category 1A Trusted Accreditation We connect the real
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0E-10
pressure sensor MATLAB program
actel rad pressure sensor
90nm cmos
RTAX250S-1000S
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a2f500m3g
Abstract: vhdl code for 8 bit ODD parity generator
Text: Core16550 v3.1 HandBook Core16550 v3.1 HandBook Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Supported Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
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Core16550
a2f500m3g
vhdl code for 8 bit ODD parity generator
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Untitled
Abstract: No abstract text available
Text: Revision 16 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)
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TM1019
MIL-STD-883B
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actel FG484 package mechanical drawing
Abstract: RTAX2000S-CQ352 actel package mechanical drawing FG484 CQ352 2-CQFP SK-AX2000-CQ352RTFG896 sk-ax FG896 rtax2000* cqfp
Text: &4 3 WR )%*$ $GDSWHU 6RFNHWV July 2004 Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 CQFP to FBGA Adapter Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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CQ352
FG484
actel FG484 package mechanical drawing
RTAX2000S-CQ352
actel package mechanical drawing
2-CQFP
SK-AX2000-CQ352RTFG896
sk-ax
FG896
rtax2000* cqfp
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56 pin edac connector
Abstract: RTAX1000 edac 96 pin edac connector 292 CCGA
Text: v2.1 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
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TM1019
56 pin edac connector
RTAX1000
edac 96 pin edac connector
292 CCGA
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RTAX2000S-CQ352
Abstract: No abstract text available
Text: RTAX-S RadTolerant FPGAs Detailed Specifications Table 2-1 • I/O Features Comparison I/O Assignment LVTTL Clamp Diode Hot Insertion / Cold Sparing 5V Tolerance No Yes No Input Buffer Output Buffer Enabled/Disabled 1 3.3 V PCI Yes No Yes Enabled/Disabled
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JESD8-11)
RTAX2000S-CQ352
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CQ352
Abstract: antifuse
Text: v2.1 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
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TM1019
CQ352
antifuse
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4x1K
Abstract: edac 96 pin edac connector footprint cqfp 132 833 T12
Text: Advanced v0.5 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETth > 60 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case
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TM1019
4x1K
edac 96 pin edac connector
footprint cqfp 132
833 T12
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Untitled
Abstract: No abstract text available
Text: CorePCIF v4.0 Handbook Microsemi Corporation, Mountain View, CA 94043 2014 Microsemi Corporation. All rights reserved. Printed in the United States of America Part Number: 50200087-7 Release: February 2014 No part of this document may be copied or reproduced in any form or by any means without prior written
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RTAX1000S-SL
Abstract: RTAX2000 actel PLL schematic LVCMOS25 signal path designer JESD8-11
Text: Application Note AC310 RTAX-S/SL Clocking Resource and Implementation Introduction Actel's RTAX-S/SL FPGA family offers the most flexible global network scheme of any antifuse-based FPGA to date. This architecture provides eight segmentable chip-wide global networks, and dedicated power-on
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AC310
RTAX1000S-SL
RTAX2000
actel PLL schematic
LVCMOS25
signal path designer
JESD8-11
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RTSX32SU CQ84
Abstract: RT3PE3000L CQ256 CQFP 256 PIN actel A54SX32A SEU RT3PE600L Cqfp256 RTAX2000 ACTEL CCGA 624 mechanical rtax2000sl aircraft logic gates
Text: System-Critical FPGAs Product Catalog November 2009 Taking Designs from Earth to Outer Space Whether you’re designing for sea-level or 2,000,000 miles into space, Actel’s high-reliability, low-power FPGAs are your best choice. With a history of providing the most reliable, robust, low-power flash and antifuse-based FPGAs in
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galois field theory
Abstract: code of encoder and decoder in rs(255,239) in vhd A3P250 APA300 RTAX250S Reed-Solomon Decoder verilog code verilog code for 8 bit shift register theory
Text: CoreRSENC v2.0 Handbook Actel Corporation, Mountain View, CA 94043 2007 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 50200106-0 Release: October 2007 No part of this document may be copied or reproduced in any form or by any means without prior written
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fpga 1553B
Abstract: 1553b VHDL MIL-STD-1553B FPGA Actel 1553b RT MIL-STD-1553B ACTEL FPGA vhdl code manchester encoder mil 1553b Core1553BRT v3.1 1553 VHDL manchester verilog decoder
Text: Core1553BRT MIL-STD-1553B Remote Terminal Product Summary • Intended Use • 1553B Remote Terminal RT • DMA Backend Interface to External Memory • Direct Backend Interface to Devices • Space and Avionic Applications • Supports MIL-STD 1553B •
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Core1553BRT
MIL-STD-1553B
1553B
1553B
1553BRT
A54SX32A
fpga 1553B
1553b VHDL
MIL-STD-1553B FPGA
Actel 1553b
RT MIL-STD-1553B ACTEL FPGA
vhdl code manchester encoder
mil 1553b
Core1553BRT v3.1
1553 VHDL
manchester verilog decoder
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PCI-M32
Abstract: design of dma controller using vhdl application of parity checker vhdl code for parity checker vhdl code it parity generator vhdl code for DMA RTAX250S vhdl code for parity generator 32 bit ALU vhdl code VHDL code for pci
Text: Flexible synthesizable VHDL PCI specification 2.3 compliant 33 MHz performance PCI-M32 32-bit datapath 32-bit/33MHz PCI Master/Target Interface Core Full bus Master/Target functio- Zero wait states burst mode nality Single interrupt support
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PCI-M32
32-bit
32-bit/33MHz
PCI-M32
design of dma controller using vhdl
application of parity checker
vhdl code for parity checker
vhdl code it parity generator
vhdl code for DMA
RTAX250S
vhdl code for parity generator
32 bit ALU vhdl code
VHDL code for pci
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RTAX2000
Abstract: RTAX2000S RTAX1000SL rtax250 RTAX250SL RTAX4000SL RTAX1000 RTAX-S RTAX1000S-SL rtax250s
Text: Rev ision 13 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)
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TM1019
MIL-STD-883B
Extended600
RTAX2000
RTAX2000S
RTAX1000SL
rtax250
RTAX250SL
RTAX4000SL
RTAX1000
RTAX-S
RTAX1000S-SL
rtax250s
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